參數(shù)資料
型號(hào)： MT9125
廠商： Mitel Networks Corporation
英文描述： Dual ADPCM Transcoder(雙ADPCM編解碼器)
中文描述： 雙差分PcM轉(zhuǎn)碼器（雙差分PcM編解碼器）
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 172K
代理商： MT9125
MT9125
Preliminary Information
8-80
Figure 6 - Pipelining for Dynamic 32/24 kb/s Operation
DSTi
ADPCMo
ENA
ENB1 or
EN1
MS1/3
MS2/4
frame n-1
frame n
frame n+1
PCM Byte "X" latched into device
during frame n-1
PCM Byte "X" processed according
to MSn input states latched during
frame n
ADPCM Word "X" output from
device during frame n+1
1,1=32 kb/s
1,0=24 kb/s
1,1=32 kb/s
This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the
reverse ADPCM to PCM direction.
Total delay from data input to data output = 2 frames. See Figure 15 for detailed ENB1/EN1 timing.
Bit Clock (BCLK)
For SSI operation the bit rate, for both ADPCM and
PCM ports, is determined by the clock input at
BCLK. BCLK must be eight periods in duration and
synchronous with the 8 kHz frame input at ENB1.
Data is sampled at DSTi and at ADPCMi concurrent
with the falling edge of BCLK. Data is available at
DSTo and ADPCMo concurrent with the rising edge
of BCLK. BCLK may be any rate between 128 kHz
and 2.048 MHz. Refer to Figures 12 and 13.
For ST-BUS operation BCLK is ignored and the bit
rate is internally set to 2.048 MHz.
PCM Law Control (A/
μ
, FORMAT)
The PCM companding/coding law invoked by the
transcoder is controlled via the A/
μ
and FORMAT
pins. CCITT G.711 companding curves,
μ
-Law and
A-Law, are determined by the A/
μ
pin (0=
μ
-
Law; 1=A-Law). Per sample, digital code assignment
can conform to CCITT G.711 (when FORMAT=1) or
to Sign-Magnitude coding (when FORMAT=0). Table
1 illustrates these choices.
Table 1
Processing Delay through the Device
One 8 kHz frame is required for serial loading of the
input buffers, and one frame is required for
processing, for a total of two frame delays through
the device. All internal input/output PCM and
ADPCM shift registers are parallel loaded through
secondary buffers on an internal frame pulse. The
device derives its internal frame reference from the
F0i, ENB1 and ENB2 pins in the following manner. If
a valid ST-BUS frame pulse is present at the F0i pin
the transcoder will assume ST-BUS operation and
will use this input as the frame reference. In this
FORMAT
0
1
PCM Code
Sign-
Magnitude
A/
μ
= 0 or 1
CCITT (G.711)
(A/
μ
= 0)
(A/
μ
= 1)
+ Full Scale
1111 1111
1000 0000
1010 1010
+ Zero
1000 0000
1111 1111
1101 0101
- Zero
0000 0000
0111 1111
0101 0101
- Full Scale
0111 1111
0000 0000
0010 1010
相關(guān)PDF資料
PDF描述
MT91600 Programmable SLIC(可編程用戶線路接口電路（在轉(zhuǎn)換系統(tǒng)和用戶環(huán)間提供一個(gè)接口）)
MT9162 5 Volt Single Rail Codec(5V 單軌編解碼器)
MT9174 ISO2-CMOS ST-BUS⑩ FAMILY Digital Network Interface Circuit with Receive Sync Marker Bit
MT9174AE ISO2-CMOS ST-BUS⑩ FAMILY Digital Network Interface Circuit with Receive Sync Marker Bit
MT9174AN ISO2-CMOS ST-BUS⑩ FAMILY Digital Network Interface Circuit with Receive Sync Marker Bit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9125AE 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Dual ADPCM Transcoder
MT9125AP 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Dual ADPCM Transcoder
MT9126 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Quad ADPCM Transcoder
MT9126AE 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Quad ADPCM Transcoder
MT9126AE1 制造商:Microsemi Corporation 功能描述:ADPCM VOICE COMPRESSION G.726 16KBPS/24KBPS/32KBPS 5V 28PDIP - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TRANSCODER QUAD ADPCM 28PDIP 制造商:Microsemi Corporation 功能描述:IC TRANSCODER QUAD ADPCM 28PDIP
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*