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參數(shù)資料
| 型號： | MT9122AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS Dual Voice Echo Canceller with Tone Detection |
| 中文描述： | CMOS雙語音回聲消除的音偵測 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 143K |
| 代理商： | MT9122AP |
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Preliminary Information
MT9122
8-33
Register Summary
Echo Canceller A, Control Register 1
Extended-
Delay
When high, Echo Cancellers A and B are internally cascaded into one 128ms echo canceller.
When low, Echo Cancellers A and B operate independently.
Do not enable both Extended-Delay and BBM configurations at the same time.
When high, echo canceller adaptation is disabled.
When low, the echo canceller dynamically adapts to the echo path characteristics.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout.
When low, output data on both Sout and Rout is a function of the echo canceller algorithm.
When high, 12dB of attenuation is inserted into the Rin to Rout path.
When low the Rin to Rout path gain is 0dB.
When high the Back to Back configuration is enabled.
When low the Normal configuration is enabled. Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers to the same logic value to avoid conflict.
When high, the noise injection process is disabled. When low noise injection is enabled.
When high, the power-up initialization is executed presetting all register bits including this bit.
AdaptDis
Bypass
PAD
BBM
INJDis
Reset
Note: Bits marked as “1” or “0” are reserved bits and should be written as indicated.
ADDRESS = 00h WRITE/READ VERIFY
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
INJDis
BBM
PAD
AdaptDis
0
Extended
Delay
Bypass
Reset
Power Reset Value
0000 0010
7
6
5
4
3
2
1
0
INJDis
BBM
PAD
AdaptDis
1
0
Bypass
Reset
Echo Canceller B, Control Register 1
ADDRESS = 20h WRITE/READ VERIFY
CRA1
CRB1
MuteR
MuteS
HPFDis
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When low, the offset nulling filters are active and will remove DC offsets on PCM input signals.
When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled.
When high, the echo canceller is in Bypass mode when the tone detectors detect the presence of 2100Hz tones. See PHDis
for qualification of 2100Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state of the 2100Hz tone detectors.
When high, the non-linear processor is disabled.
When low, the non-linear processors function normally. Useful for G.165 conformance testing.
When high, the tone detectors will trigger upon the presence of a 2100Hz tone regardless of the presence/absence of periodic
phase reversals.
When low, the tone detectors will trigger only upon the presence of a 2100Hz tone with periodic phase reversals.
When high, tone detection is disabled entirely. When low, tone detection is enabled.
NBDis
AutoTD
NLPDis
PHDis
TDis
Echo Canceller A, Control Register 2
Echo Canceller B, Control Register 2
ADDRESS = 01h WRITE/READ VERIFY
ADDRESS = 21h WRITE/READ VERIFY
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
PHDis
NLPDis
AutoTD
HPFDis
MuteS
MuteR
NBDis
TDis
CR2
NB
TDG
Logic high indicates the presence of a narrow-band signal on Rin.
Tone detection status bit gated with the AutoTD bit.
Logic high indicates that AutoTD has been enabled and the tone detector has detected the presence of a 2100Hz tone.
Logic high indicates that the power level on Rin is above the threshold level (i.e., low power condition).
Decision indicator for the non-linear processor gain adjustment.
Decision indicator for rapid adaptation convergence. Logic high indicates a rapid convergence state.
Logic high indicates the presence of a double-talk condition.
Logic high indicates the presence of a 2100Hz tone.
Active
Down
Conv
DTDet
TD
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
TD
DTDet
Conv
Active
TDG
NB
Echo Canceller A, Status Register
Echo Canceller B, Status Register
ADDRESS = 02h READ
ADDRESS = 22h READ
Down
SR
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PDF描述 |
|---|---|
| MT9123AE | CMOS Dual Voice Echo Canceller |
| MT9123 | Dual Voice Echo Canceller(雙話音回聲消除器) |
| MT9123AP | CMOS Dual Voice Echo Canceller |
| MT9125AE | CMOS Dual ADPCM Transcoder |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9122AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:ECHO CANCELLER CHIP 2CH G.164/G.165/G.711 W/ TONE DETECTION - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DUAL VOICE ECHO CANCELLER W/TD |
| MT9122APR1 | 制造商:Zarlink Semiconductor Inc 功能描述:ECHO CANCELLER CHIP 2CH G.164/G.165/G.711 W/ TONE DETECTION - Tape and Reel |
| MT9123 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Dual Voice Echo Canceller |
| MT9123AE | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.165/G.711 W/OUT TONE DETECTION 28P - Rail/Tube |
| MT9123AE1 | 制造商:Microsemi Corporation 功能描述: |
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