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參數(shù)資料
| 型號(hào)： | MT9094 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Digital Telephone (DPhone-II)(數(shù)字電話) |
| 中文描述： | 數(shù)字電話（DPhone -Ⅱ）（數(shù)字電話） |
| 文件頁數(shù)： | 2/34頁 |
| 文件大小： | 234K |
| 代理商： | MT9094 |
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MT9094
7-46
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
M+
Non-Inverting Microphone (Input).
Non-inverting input to microphone amplifier from the
handset microphone.
2
NC
No Connect.
No internal connection to this pin.
3
V
Bias
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1
μ
F capacitor to V
SSA
.
Reference voltage for codec (Output).
Nominally [(V
DD
/2)-1.5] volts. Used internally.
Connect 0.1
μ
F capacitor to V
SSA
.
Internal Connection.
Tie externally to V
SS
for normal operation.
PWRST
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
4
V
Ref
5
IC
6
7
DSTi
ST-BUS Serial Stream (Input).
2048 kbit/s input stream composed of 32 eight bit channels;
the first four of which are used by the MT9094. Input level is TTL compatible.
8
DSTo
ST-BUS Serial Stream (Output).
2048 kbit/s output stream composed of 32 eight bit
channels. The MT9094 sources digital signals during the appropriate channel, time coincident
with the channels used for DSTi.
9
C4i
4096 kHz Clock (Input).
CMOS level compatible.
10
F0i
Frame Pulse (Input).
CMOS level compatible. This input is the frame synchronization pulse
for the 2048 kbit/s ST-BUS stream.
11
V
SSD
NC
Digital Ground.
Nominally 0 volts.
12
No Connect.
No internal connection to this pin.
13
SCLK
Serial Port Synchronous Clock (Input).
Data clock for MCS-51 compatible microport. TTL
level compatible.
1
6
5
4
3
2
4
4
4
4
4
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
2
1
1
2
2
2
2
2
2
2
2
P
I
V
V
N
M
V
M
M
M
DSTi
DSTo
C4i
F0i
VSSD
NC
SCLK
DATA 2
DATA 1
CS
WD
SPKR+
SPKR-
HSPKR+
HSPKR-
VDD
BP
S12
S11
S10
S9
S8
I
N
N
V
S
S
S
S
S
S
S
44 PIN PLCC
V
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