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參數(shù)資料
| 型號： | MT90871AV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 8K Digital Switch (F8KDX) |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA196 |
| 封裝： | 15 X 15 MM, 1 MM PITCH, LBGA-196 |
| 文件頁數(shù)： | 7/65頁 |
| 文件大?。?/td> | 639K |
| 代理商： | MT90871AV |
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Data Sheet
MT90871
7
Zarlink Semiconductor Inc.
ODE
B9
Output Drive Enable (5V Tolerant, Internal pull-up).
An asynchronous input providing Output Enable control to the BSTo0-15,
LSTo0-15, BCSTo0-1 and LCSTo0-1 outputs.
When LOW, the BSTo0-15 and LSTo0-15 outputs are driven high or high
impedance (dependent on the
BORS
and
LORS
pin settings respectively)
and the outputs BCSTo0-1 and LCSTo0-1 are driven low.
When HIGH, the outputs BSTo0-15, LSTo0-15, BCSTo0-1 and LCSTo0-1
are enabled.
Backplane Output Reset State (5V Tolerant, Internal pull-down).
Asynchronous input. When LOW, the device will initialize with the BSTo0-
15 outputs driven high, and the BCSTo0-1 outputs driven low. Following
initialization, the Backplane stream outputs are always active and a high
impedance state, if required on a per-channel basis, may be implemented
with external buffers controlled by outputs BCSTo0-1.
BORS
G2
When the input is HIGH, the device will initialize with the BSTo0-15 outputs
at high impedance and the BCSTo0-1 outputs are driven low. Following
initialization, the Backplane stream outputs may be set active or high
impedance using the
ODE
pin or, on a per-channel basis, with the
BE
bit in
Backplane Connection Memory.
Backplane Output Reset State (5V Tolerant, Internal pull-down).
Asynchronous input. When LOW, the device will initialize with the LSTo0-
15 outputs driven high, and the LCSTo0-1 outputs driven low. Following
initialization, the Backplane stream outputs are always active and a high
impedance state, if required on a per-channel basis, may be implemented
with external buffers controlled by outputs LCSTo0-1.
LORS
H13
When the input is HIGH, the device will initialize with the LSTo0-15 outputs
at high impedance and the LCSTo0-1 outputs are driven low. Following
initialization, the Backplane stream outputs may be set active or high
impedance using the
ODE
pin or, on a per-channel basis, with the
LE
bit in
Backplane Connection Memory.
No Connect.
These ball-pads MUST remain unconnected.
Internal Connect
s
These inputs MUST be held at logic ‘LOW’.
NC
IC
P9, P11
C1, D1, C11, C13,
M7, M8, N8, P8
Pin Description Table (continued)
Name
Package
Coordinates
Description
相關PDF資料 |
PDF描述 |
|---|---|
| MT90871 | Flexible 8K Digital Switch (F8KDX) |
| MT90883 | TDM to Packet Processors |
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
| MT91600AN1 | Programmable SLIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90880 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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