參數(shù)資料
型號(hào): MT90826AV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Quad Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA144
封裝: 13 X 13 MM, 1.25 MM HEIGHT, MO-192, LBGA-144
文件頁數(shù): 6/46頁
文件大?。?/td> 571K
代理商: MT90826AV
MT90826
Data Sheet
6
Zarlink Semiconductor Inc.
Changes Summary
The following table captures the changes from the April 2005 issue.
Page
Item
Change
26
Figure 6 “Examples for Input Offset
Delay Timing”
Clarified the mid-point sampling of the 16Mbps input
data.
30
Section 9.0 Initialization of the
MT90826
Added the 600
μ
s waiting time needed for the APLL
module to be stabilized before starting the next
microprocessor port access cycle.
37
AC Electrical Characteristics - Serial
Streams for ST-BUS.
Clarified the 16, 8, 4 and 2 Mbps Input Data Sampling
timing.
37
Figure 8 “ST-BUS Timing for Stream
rate of 16.384 Mbps”
Clarified the input data sampling position at 16 Mbps
data rate.
38
Figure 9 “ST-BUS Timing for Stream
rate of 8.192 Mbps when CLK =
16.384 MHz”
Added the input data sampling position at 8 Mbps data
rate.
38
Figure 10 “ST-BUS Timing for Stream
rate of 4.096 Mbps when CLK =
16.384 MHz”
Added the input data sampling position at 4 Mbps data
rate.
39
Figure 12 “ST-BUS Timing for Stream
rate of 2.048 Mbps when CLK =
16.384 MHz”
Added the input data sampling position at 2 Mbps data
rate.
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參數(shù)描述
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