參數(shù)資料
型號(hào)： MT90810
廠商： Mitel Networks Corporation
英文描述： Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路)
中文描述： 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路）
文件頁(yè)數(shù)： 3/33頁(yè)
文件大?。?/td> 176K
代理商： MT90810
Preliminary Information
MT90810
2-171
92
EX_8KB
External 8kHz input B (TTL Input).
94
FRAME
Local Frame Output Signal (Output).
This 8kHz framing signal has a duty cycle and
period equal to the MVIP F0 signal.
95
CLK8
8MHz Local Output Clock (Output). This is a 8MHz clock.
97
CLK4
4MHz Local Output Clock (Output). This 4MHz clock has a duty cycle and period equal
to the MVIP C4 signal.
98
CLK2
2MHz Local Output Clock (Output). This 2MHz clock has a duty cycle and period equal
to the MVIP C2 signal.
100, 1,
2, 3, 5,
20, 33,
46, 57,
69, 81,
96
FGA[0:11]
Frame Group A framing signals (Output).
Programmable framing signals. The frame
group outputs are determined by mode bits in the frame register to be either
programmed outputs, output drive enables for DSo, or output framing pulses for use
with local serial data streams.
6, 7, 8,
9, 14,
28, 39,
51, 62,
76, 84,
99
FGB[0:11]
Frame Group B framing signals (Output).
Programmable framing signals. The frame
group outputs are determined by mode bits in the frame register to be either
programmed outputs, output drive enables for DSi, or output framing pulses for use with
local serial data streams.
19
RESET
Chip Reset (Schmitt Input).
This active low reset clears all internal registers, except
connection memory and data memory.
35, 36,
37, 38,
42, 43,
44, 45
AD[0:7]
Microprocessor Address/Data Bus (Bidirectional TTL).
Microprocessor access to
internal registers, connection and data memories.
In non-multiplexed mode: data bus.
In multiplexed mode: multiplexed address and data bus.
32, 34
A[0:1]
Microprocessor Address (TTL Input).
In non-multiplexed mode: address to FMIC internal registers
In multiplexed mode: unused (leave unconnected).
29
ALE
Microprocessor Address Latch Enable (TTL Input).
Selects the microprocessor
mode.
In Intel multiplexed mode, the falling edge of this signal is used to sample the address.
27
CS
Microprocessor Bus Chip Select (TTL Input).
This active low input enables
microprocessor access to connection and data memory and internal registers.
26
RD/[DS]
Read/Data Strobe (TTL Input).
In Intel mode (RD), this active low input configures the data bus lines as output.
In Motorola mode (DS), this active low input operates with CS to enable read and write
operation.
25
WR/[R/W]
Write\ Read/Write Strobe (TTL Input).
In Intel mode (WR), this active low input configures the data bus lines as inputs.
In Motorola mode (R/W), this input controls the direction of the data bus D[0:7] during a
microprocessor access.
30
RDY
[DTACK]
Ready/Data Acknowledge (Open Drain Output).
In Intel mode (RDY), this output acts as IOCHRDY. A 10K pull up is required.
In Motorola mode (DTACK), this active low output indicates a successful data bus
transfer. A 10K pull up is required.
Pin Description (continued)
Pin #
Name
Description
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