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參數(shù)資料
| 型號： | MT9080B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | SMX - Switch Matrix Module(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊) |
| 中文描述： | SMX -開關(guān)矩陣模塊（用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊） |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 123K |
| 代理商： | MT9080B |
MT9080B
CMOS
2-106
Figure 4 - Data Memory Mode Functional Timing
Figure 5 - Throughput Delay in Data Memory Mode-1
CK
External
Address
Bus A0-A15
Data Output
D0-D15o
FP
Address
generated by
Internal 11
Bit Counter
Data Input
D0-D15i
CH X
CH Y
CH Z
1022
1023
0
1
2
1
0
1023
Counter Reset
CH X
CH Y
CH Z
P
W
P
R
y
P = Precharge
R = Read Memory
W = Write Memory
Data is clocked out of the memory location addressed by external address bus. The address is latched in with CK edge
marked
. Data is clocked out with CK edge marked
y
.
Data is latched into the device with the last rising edge of CK in the timeslot (e.g., edge
in diagram). It is stored in the
memory location address by the internal 11 bit counter with the next rising clock edge (edge
in diagram).
CK
P
W
R
y
P
1
4
1
2
3
4
5
2
3
P = Precharge
R = Read Memory
W = Write Memory
Data on the input bus of the SMX is latched into the device with last rising edge of the clock within a timeslot. It is
written into the internal memory with the following positive edge.
Data is clocked out of the memory location and latched onto the output data bus with first positive clock edge in the
timeslot.
Input
Data
Output
Timeslots
Switching channel 1 to channel 1 or channel 2 will result in one frame delay. Note that channel 2 is clocked out by CK
edge labelled
while channel 1 is written into the memory with edge
y
. However, if channel 1 is switched to channel
3, there will be only one channel delay.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90810AK | 制造商:Microsemi Corporation 功能描述: |
| MT90812 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
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