參數(shù)資料
型號: MT9080B
廠商: Mitel Networks Corporation
英文描述: SMX - Switch Matrix Module(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊)
中文描述: SMX -開關(guān)矩陣模塊(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊)
文件頁數(shù): 11/25頁
文件大小: 123K
代理商: MT9080B
CMOS
MT9080B
2-111
memory. The delay through the matrix can be
optimized for specific applications by selectively
enabling one of the two modes. Data Memory-1
(DM-1) is designed for voice switching applications
where it is generally desirable to minimize delay
through the switch. As mentioned earlier in the DM-1
description, the delay through the switch depends
upon the difference between the input channel
timeslot
and
the
output
Consecutive
output
channels
non-contiguous input channels will not always
originate from the same input frame. For example, if
channels 3, 6 and 8 are to be switched to channels 5,
6 and 7; output channel 5 will contain data input in
the current frame, while channels 6 and 7 will contain
data clocked in one frame earlier. Data Memory-2
channel
switched
timeslot.
from
(DM-2) is designed for data switching applications
where concatenation of a number of channels is
often necessary. Data clocked out of the device will
originate from the previous frame, regardless of the
input/output time difference. There is one exception,
when channel 1023 is switched to channel 0, the
contents of Channel 0 will not originate from the
previous frame but rather from the frame before it.
The capability to selectively change between DM-1
and DM-2 allows a single switch to handle both voice
and data effectively.
External bus drivers can be controlled with D13 of
the Connection Memory data bus. This bit will be
output along with the remaining bits one channel
Figure 15 - 1024 Channel Switch Matrix
Parallel Input Data
Parallel Output Data
16
16
D0
i
-D15
i
D0
o
-D15
o
SMX #1
DM-1/2
DATA
MEMORY
A10-A15
R/W
CS
DS
FP
CK
A0-A9
ODE
ME
Z
Y
X
MODE
10
+5
External
Tristate
Control
Timing
Generator
FP#1
CK
FP#2
D0
o
-D9
o
D10
o
D11
o
D12
o
D13
o
X
Y
Z
MODE
A11-A15
A10
CS
CK
FP
CD
D0-D15
R/W
DTA
DS
A0-A9
SMX #2
CM-1
CONNECTION
MEMORY
0
1
0
+5
Address
Decode
D0-D15
R/W
HALT
DS
IRQ
16-BIT MPU
Note: All other inputs not shown in this diagram should be connected to GND.
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