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參數(shù)資料
| 型號： | MT90710AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | High-Speed Isochronous Multiplexer |
| 中文描述： | 高速同步復用器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 113K |
| 代理商： | MT90710AP |
Preliminary Information
MT90710
5-7
Notes:
All unused inputs should be connected to logic high or low unless otherwise stated. All outputs should be left open circuit when not used.
All output types are CMOS with CMOS logic levels (see DC Electrical Characteristics for Type drive capability).
Input Type 1 has TTL compatible logic levels, Type 2 has CMOS compatible logic levels and Type 3 has TTL Schmitt trigger compatible
logic levels (see DC Electrical Characteristics).
62
DIN32K
Asynchronous 32 kHz Signal (Input Type 1).
Transmitted to the far-end DOUT32K
output.
63
V
DD
V
SS
Positive Power Supply.
Nominally 5 volts.
64
Power Supply Ground
. Nominally 0 volts.
65
FBDATA3
Frame Buffer Data Bit 3 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 3.
66
STi0
Serial, 32 Channel, 2.048 Mb/s Link 0 (Input Type 1).
67
FBDATA2
Frame Buffer Data Bit 2 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 2.
68
DIN8K1
Asynchronous 8 kHz Signal 1 (Input Type 1).
Transmitted to the far-end DOUT8K1
output.
69
FBDATA1
Frame Buffer Data Bit 1 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 1.
70
LLED
"Local Sync" LED Driver (Open Collector, Output Type 2).
Drives the "Local Sync"
LED on/off at approximately a 4 Hz rate when the local interface is not in
synchronization.
71
FBDATA0
Frame Buffer Data Bit 0 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 0.
72
RESET
Reset Control (Input Type 1).
73
IC
Internally Connected.
74
V
DD
NC
Positive Power Supply.
Nominally 5 volts.
75
No Internal Connection.
76
V
SS
Power Supply Ground
. Nominally 0 volts.
77
FBADDR0
Frame Buffer RAM Address Bit 0 (Output Type 2).
78
FBADDR1
Frame Buffer RAM Address Bit 1 (Output Type 2).
79
FBADDR2
Frame Buffer RAM Address Bit 2 (Output Type 2).
80
FBADDR3
Frame Buffer RAM Address Bit 3 (Output Type 2).
81
FBADDR4
Frame Buffer RAM Address Bit 4 (Output Type 2).
82
FBADDR5
Frame Buffer RAM Address Bit 5 (Output Type 2).
83
FBADDR6
Frame Buffer RAM Address Bit 6 (Output Type 2).
84
STo6B
Serial, 32 Channel, 2.048 Mb/s Link 6B (Output Type 3).
Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.
Pin Description
Pin #
Name
Description
Overview
The MT90710 multiplexes multiple Serial Telecom
(ST-BUS timing, Figure 7) links onto a single 20 MHz
loop to facilitate point-to-point data transport
requirements. The MT90710 connects easily with
standard Fiber Optic interfaces to form a complete
electric to photonic conversion circuit. Optical
transmission allows large bandwidth inter-shelf or, in
distributed systems, inter-node communication by
eliminating multiple data busses, cable inter-connect
and the attendant driver interfaces. The final result is
a simple physical interface free of the radiated
emissions and background noise susceptibility
problems
encountered
environments.
in
copper-wired
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