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參數(shù)資料
| 型號： | MT90710AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | High-Speed Isochronous Multiplexer |
| 中文描述： | 高速同步復(fù)用器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 113K |
| 代理商： | MT90710AP |
Preliminary Information
MT90710
5-5
10
STo5
Serial, 32 Channel, 2.048 Mb/s Link 5 (Output Type 3).
Output is active only when
the receiver detects the synchronization pattern on RxDATA input stream; output is high
impedance during loss of synchronization.
11
V
DD
V
SS
C4o
Positive Power Supply.
Nominally 5 volts.
12
Power Supply Ground
. Nominally 0 volts.
13
4.096 MHz Clock (Output Type 3).
Used by the transmit PLL. This clock is the input
C40i (40.96MHz, see pin 18) master clock divided by 10 (inverted) and is fed back to
the external PLL circuit as a reference.
14
C4REFo
4.096 MHz Reference Clock (Output Type 3).
Used by transmit PLL. When in control-
ler mode this clock is derived from the system C4b (4.096 MHz) clock input (see pin
57). When in peripheral mode this clock is extracted from the receive data on the fiber
port.
15,16,
17
NC
No Internal Connection.
18
C40i
Transmit 40.96 MHz Clock (Input Type 2).
Derived from the transmit PLL. This is the
master clock used by the device.
19
STi1
Serial, 32 Channel, 2.048 Mb/s Link 1 (Input Type 1).
20
STi2
Serial, 32 Channel, 2.048 Mb/s Link 2 (Input Type 1).
21
V
SS
V
DD
STi3
Power Supply Ground
. Nominally 0 volts.
22
Positive Power Supply.
Nominally 5 volts.
23
Serial, 32 Channel, 2.048 Mb/s Link 3 (Input Type 1).
24
STi4
Serial, 32 Channel, 2.048 Mb/s Link 4 (Input Type 1).
25
STi5
Serial, 32 Channel, 2.048 Mb/s Link 5 (Input Type 1).
26
STi6A
Serial, 32 Channel, 2.048 Mb/s Link 6A (Input Type 1).
27
STi6B
Serial, 32 Channel, 2.048 Mb/s Link 6B (Input Type 1).
28
STi7
Serial, 32 Channel, 2.048 Mb/s Link 7 (Input Type 1).
Only channels 9 - 31 are avail-
able for user data transfer (1.472 Mb/s). Data input on channels 0 - 8 (0.576 Mb/s) is
ignored by the device. This bandwidth is reserved for fiber overhead information.
29
E20i
Receiver 20.96 MHz Clock (Input Type 2).
Extracted clock from the receive data
stream. Divided internally by 5 and phase corrected to frame synch pattern to produce
internal 2.048 MHz data clock for parsing the receive STi streams.
30
NC
No Internal Connection.
31
V
SS
NC
Power Supply Ground
. Nominally 0 volts.
32
No Internal Connection.
33
V
DD
NC
Positive Power Supply.
Nominally 5 volts.
34
No Internal Connection
.
35
RxDATA
Receive 4B/5B, NRZI Encoded Serial Data (Input Type 1).
36
RLED
"Remote Sync" LED Driver (Open Collector, Output Type 3).
Drives the "Remote
Sync" LED on/off at approximately a 4 Hz rate when the remote interface is not syn-
chronized. Active only when the local interface is synchronized.
37
FBOE
Frame Buffer Ram Enable (Output Type 2).
Generates a low going strobe during
valid RAM read access.
Pin Description
Pin #
Name
Description
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