- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359234 > MT9045 (Zarlink Semiconductor Inc.) T1/E1/OC3 System Synchronizer PDF資料下載
參數(shù)資料
| 型號(hào)： | MT9045 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | T1/E1/OC3 System Synchronizer |
| 中文描述： | T1/E1/OC3系統(tǒng)同步 |
| 文件頁數(shù)： | 16/34頁 |
| 文件大?。?/td> | 495K |
| 代理商： | MT9045 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
MT9045
Data Sheet
16
Zarlink Semiconductor Inc.
MT9045 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference
within approximately 500 ms.
MT9045 and Network Specifications
The MT9045 fully meets all applicable PLL requirements (intrinsic jitter/wander, jitter/wander tolerance,
jitter/wander transfer, frequency accuracy, frequency holdover accuracy, capture range, phase change slope and
MTIE during reference rearrangement) for the following specifications.
1. Bellcore GR-1244-CORE June 1995 for Stratum 3, Stratum 4 Enhanced and Stratum 4
2. AT&T TR62411 (DS1) December 1990 for Stratum 3, Stratum 4 Enhanced and Stratum 4
3. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4
4. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. TU-T I.431 March 1993
9. TU-T G.813 August 1996 for Option1 clocks for 2048 kbit/s interfaces
10. ITU-T G.812 June 1998 for type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces
Applications
This section contains MT9045 application specific details for clock and crystal operation, reset operation, power
supply decoupling, and control operation.
Master Clock
The MT9045 can use either a clock or crystal as the master timing source.
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source
at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source
may be
±
100ppm. For applications requiring an accurate Freerun Mode, such as AT&T TR62411, the tolerance of
the master timing source must be no greater than
±
32ppm.
Another consideration in determining the accuracy of the master timing source is the desired capture range. The
sum of the accuracy of the master timing source and the capture range of the MT9045 will always equal 230ppm.
For example, if the master timing source is 100ppm, then the capture range will be 130ppm.
Clock Oscillator
- when selecting a Clock Oscillator, numerous parameters must be considered. This includes
absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9045AN | T1/E1/OC3 System Synchronizer |
| MT9046 | T1/E1 System Synchronizer with Holdover |
| MT9046AN | T1/E1 System Synchronizer with Holdover |
| MT90503 | 2048VC AAL1 SAR |
| MT90503AG | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9045AN | 制造商:Microsemi Corporation 功能描述: |
| MT9045AN1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Rail/Tube 制造商:Microsemi Corporation 功能描述:T1/E1/OC3 SYSTEM SYNCHRONIZER |
| MT9045ANR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Tape and Reel 制造商:Microsemi Corporation 功能描述:iB FREE T1/E1/OC3 SYSTEM SYNCHRONIZER 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Tape and Reel |
| MT9046 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| MT9046AN | 制造商:Microsemi Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。