
Advance Information
MT9043
7
The frame pulse outputs (F0o, F8o, F16o, TSP, and
RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a
common DPLL signal. Consequently, all frame pulse
and clock outputs are locked to one another for all
operating states, and are also locked to the selected
input reference in Normal Mode. See Figures 13 &
14.
All frame pulse and clock outputs have limited driving
capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL for
a complete loss of incoming signal, or a large
frequency shift in the incoming signal. If the input
signal is outside the Impairment Monitor Capture
Range the PLL automatically changes from Normal
Mode
to
Free
Run
Mode.
Characteristics - Performance for the Impairment
Monitor Capture Range. When the incoming signal
returns to normal, the DPLL is returned to Normal
Mode.
See
AC
Electrical
State Machine Control
As shown in Figure 1, this state machine controls the
Reference Select MUX, the TIE Corrector Circuit and
the DPLL. Control is based on the logic levels at the
control inputs RSEL and MS (See Figure 6).
All state machine changes occur synchronously on
the rising edge of F8o. See the Control and Mode of
Operation section for full details.
Figure 6 - Control State Machine Block Diagram
Master Clock
The MT9043 can use either a clock or crystal as the
master timing source. For recommended master
timing circuits, see the Applications - Master Clock
section.
Control and Mode of Operation
The MT9043 has two possible modes of operation,
Normal and Freerun.
As shown in Table 3, the Mode/Control Select pin MS
selects the mode.
The active reference input (PRI or SEC) is selected
by the RSEL pin as shown in Table 2. Refer to Table
4 and Figure 7 for details of the state change
sequences.
Normal Mode
Normal Mode is typically used when a slave clock
source, synchronized to the network is required.
In Normal Mode, the MT9043 provides timing (C1.5o,
C2o,
C4o,
C8o,
C16o
synchronization (F0o, F8o, F16o, TSP and RSP)
signals, which are synchronized to one of two
reference inputs (PRI or SEC). The input reference
signal may have a nominal frequency of 8kHz,
1.544MHz, 2.048MHz or 19.44MHz.
and
C19o)
and
frame
From a reset condition, the MT9043 will take up to 30
seconds (see AC Electrical Characteristics) of input
reference
signal
to
output
synchronized (phase locked) to the reference input.
signals
which
are
The
dependent as shown in state table 4. The reference
frequencies are selected by the frequency control
pins FS2 and FS1 as shown in Table 1.
selection
of
input
references
is
control
Fast Lock Mode
Fast Lock Mode is a submode of Normal Mode, it is
used to allow the MT9043 to lock to a reference more
quickly than Normal mode will allow. Typically, the
MS
To
Reference
Select MUX
To TIE
Corrector
Enable
Control
State Machine
To DPLL
State
Select
RSEL
RSEL
Input Reference
0
PRI
1
SEC
Table 2 - Input Reference Selection
MS
Mode
0
NORMAL
1
FREERUN
Table 3 - Operating Modes and States