參數(shù)資料
型號(hào)： MT9043
廠(chǎng)商： Mitel Networks Corporation
英文描述： T1/E1 System Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
中文描述： T1/E1的系統(tǒng)同步（T1/E1的系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成））
文件頁(yè)數(shù)： 6/24頁(yè)
文件大?。?/td> 100K
代理商： MT9043
MT9043
Advance Information
6
DPLL. The two possible modes are Normal and
Freerun.
Digitally Controlled Oscillator (DCO)
- the DCO
receives the limited and filtered signal from the Loop
Filter,
and
based
on
corresponding
digital
synchronization method of the DCO is dependent on
the state of the MT9043.
its
value,
generates
signal.
a
output
The
In Normal Mode, the DCO provides an output signal
which is frequency and phase locked to the selected
input reference signal.
In Freerun Mode, the DCO is free running with an
accuracy equal to the accuracy of the OSCi 20MHz
source.
Lock Indicator
- If the PLL is in frequency lock
(frequency lock means the center frequency of the
PLL is identical to the line frequency), and the input
phase offset is small enough such that no phase
slope limiting is exhibited, then the lock signal will be
set high.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output
Interface Circuit to provide the output signals shown
in Figure 5. The Output Interface Circuit uses four
Tapped Delay Lines followed by a T1 Divider Circuit,
an E1 Divider Circuit, and a DS2 Divider Circuit to
generate the required output signals.
Four tapped delay lines are used to generate
16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz
signals.
The E1 Divider Circuit uses the 16.384MHz signal to
generate four clock outputs and five frame pulse
outputs.
generated by simply dividing the C16o clock by two,
four and eight respectively. These outputs have a
nominal 50% duty cycle.
The
C8o,
C4o
and
C2o
clocks
are
The T1 Divider Circuit uses the 12.384MHz signal
to generate the C1.5o clock by dividing the internal
C12 clock by eight. This output has a nominal 50%
duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal
to generate the clock output C6o. This output has a
nominal 50% duty cycle.
Figure 5 - Output Interface Circuit Block
Diagram
Tapped
Delay
Line
From
DPLL
T1 Divider
E1 Divider
16MHz
12MHz
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Tapped
Delay
Line
Tapped
Delay
Line
Tapped
Delay
Line
DS2 Divider
12MHz
19MHz
C6o
C19o
Figure 4 - DPLL Block Diagram
Control
Circuit
State Select
from
Input Impairment Monitor
State Select
from
State Machine
Feedback Signal
from
Frequency Select MUX
DPLL Reference
to
Output Interface Circuit
Virtual Reference
from
TIE Corrector
Limiter
Loop Filter
Digitally
Controlled
Oscillator
Phase
Detector
相關(guān)PDF資料
PDF描述
MT9044 T1/E1/OC3 System Synchronizer(T1/E1/OC3 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
MT90500 Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）)
MT90500 Multi-Channel ATM AAL1 SAR
MT90500AL Multi-Channel ATM AAL1 SAR
MT90502 Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9043AN 制造商:Microsemi Corporation 功能描述:
MT9043AN1 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:FRAMER E1/T1 3.3V 48SSOP - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER T1/E1 48SSOP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER T1/E1 48SSOP
MT9043AN48PINSSOP 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1 System Synchronizer
MT9043ANR1 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER T1/E1 48SSOP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER T1/E1 48SSOP
MT9044 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:T1/E1/OC3 System Synchronizer
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