參數(shù)資料
型號(hào)： MT9042AP
廠商： Mitel Networks Corporation
英文描述： Global Digital Trunk Synchronizer
中文描述： 全球數(shù)字集群同步
文件頁(yè)數(shù)： 2/16頁(yè)
文件大小： 122K
代理商： MT9042AP
MT9042
Preliminary Information
3-98
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
V
SS
TRST
Negative Power Supply Voltage.
Nominally 0 Volts.
2
TIE Circuit Reset (TTL compatible).
When HIGH, the time interval error correction circuit is
alternately establishing the phase difference between the PRI and SEC reference inputs,
depending upon which input is selected as input for PLL synchronization. This information is
used to generate a virtual reference for input to the PLL. When LOW, the time interval error
correction circuit is bypassed.
3
SEC
Secondary Reference Input (TTL compatible).
This input (either 8 kHz, 1.544 MHz, or
2.048 MHz as controlled by the input frequency selection pins) is used as an alternate
reference source for PLL synchronization.
4
PRI
Primary Reference Input (TTL compatible).
This input (either 8 kHz, 1.544 MHz, or 2.048
MHz as controlled by the input frequency selection pins) is used as the primary reference
source for PLL synchronization.
5
V
DD
MCLKo
Positive Supply Voltage.
Nominally +5 volts.
6
Master Clock Oscillator Output.
This is a CMOS buffered output used for driving a 20 MHz
crystal.
7
MCLKi
Master Clock Oscillator Input.
This is a CMOS input for a 20 MHz crystal or crystal
oscillator. Signals should be DC coupled to this pin.
8
FP8-GCI
Frame Pulse Output (CMOS compatible).
This is an 8 kHz output framing pulse that
indicates the start of the active GCI-BUS frame. The pulse width is based upon the period of
the 8.192 MHz synchronization clock.
9
F0o
Frame Pulse Output (CMOS compatible).
This is an 8 kHz output framing pulse that
indicates the start of the active ST-BUS frame. The pulse width is based upon the period of
the 4.096 MHz synchronization clock. This is an active low signal.
10
FP8-STB
Frame Pulse Output (CMOS compatible).
This is an 8 kHz output framing pulse that
indicates the start of the active ST-BUS frame. The pulse width is based upon the period of
the 8.192 MHz synchronization clock.
11
C1.5
Clock 1.544 MHz (CMOS compatible).
This ouput is a 1.544 MHz (T1) output clock locked
to the selected reference input signal.
12
C3
Clock 3.088 MHz (CMOS compatible).
This output is a 3.088 MHz output clock locked to
the selected reference input signal.
1
6
7
8
9
10
11
12 13 14 15 16 17 18
5
4
3
2
23
22
19
20
21
24
25
26
27
28
V
T
S
P
VDD
MCLKo
MCLKi
FP8-GCI
F0o
FP8-STB
C1.5
GTi
GTo
LOSS2
LOSS1
MS2
MS1
RSEL
F
F
R
C
V
C
C
V
C
C
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