參數(shù)資料
型號(hào): MT9040
廠商: Mitel Networks Corporation
英文描述: T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置(由一個(gè)數(shù)字鎖相環(huán)組成))
中文描述: 的T1/E1同步(T1/E1的系統(tǒng)同步裝置(由一個(gè)數(shù)字鎖相環(huán)組成))
文件頁(yè)數(shù): 7/20頁(yè)
文件大?。?/td> 82K
代理商: MT9040
Advance Information
MT9040
7
given
amplitude) are the same.
input
signal
(jitter
frequency
and
jitter
Since
attenuation will appear to be lower for small input
jitter signals than for large ones. Consequently,
accurate jitter transfer function measurements are
usually made with large input jitter signals (e.g., 75%
of the specified maximum jitter tolerance).
intrinsic
jitter
is
always
present,
jitter
Frequency Accuracy
Frequency accuracy is defined as the absolute
tolerance of an output clock signal when it is not
locked to an external reference, but is operating in a
free running mode. For the MT9040, the Freerun
accuracy is equal to the Master Clock (OSCi)
accuracy.
Capture Range
Also referred to as pull-in range. This is the input
frequency range over which the synchronizer must
be able to pull into synchronization. The MT9040
capture range is equal to
±
230 ppm minus the
accuracy of the master clock (OSCi). For example, a
32 ppm master clock results in a capture range of 198
ppm.
Lock Range
This is the input frequency range over which the
synchronizer
must
be
synchronization. The lock range is equal to the
capture range for the MT9040.
able
to
maintain
Phase Lock Time
This is the time it takes the synchronizer to phase
lock to the input signal. Phase lock occurs when the
input signal and output signal are not changing in
phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is
affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
Although a short lock time is desirable, it is not
always possible to achieve due to other synchronizer
requirements. For instance, better jitter transfer
performance is achieved with a lower frequency loop
filter which increases lock time. See AC Electrical
Characteristics - Performance for Maximum Phase
Lock Time.
MT9040 provides a fast lock pin (FLOCK), which,
when set high enables the PLL to lock to an
incoming reference within approximately 500 ms.
MT9040 and Network Specifications
The
requirements (intrinsic jitter, jitter/wander tolerance,
jitter/wander
transfer,
frequency
capture range for the following specifications.
MT9040
fully
meets
all
applicable
PLL
accuracy
and
1. Bellcore GR-1244-CORE June 1995 for Stratum 4
2. AT&T TR62411(DS1) December 1990 for
Stratum 4
3. ANSI T1.101 (DS1) February 1994 for
Stratum 4
4. ETSI 300 011 (E1) April 1992
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993
相關(guān)PDF資料
PDF描述
MT9041A ()
MT9041B T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置(由一個(gè)數(shù)字鎖相環(huán)組成))
MT9042B ()
MT9042C Multitrunk System Synchronizer(多中繼系統(tǒng)同步裝置)
MT9043 T1/E1 System Synchronizer(T1/E1 系統(tǒng)同步裝置(由一個(gè)數(shù)字鎖相環(huán)組成))
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