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參數(shù)資料
| 型號： | MT9040 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| 中文描述： | 的T1/E1同步（T1/E1的系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）） |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 82K |
| 代理商： | MT9040 |
3
Advance Information
MT9040
14
TSP
Transmit Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 11.
15
F8o
Frame Pulse (CMOS Output).
This is an 8kHz 122ns active high framing pulse, which marks
the beginning of a frame. See Figure 10.
16
C1.5o
Clock 1.544MHz (CMOS Output).
This output is used in T1 applications.
18
LOCK
Lock Indicator (CMOS Output).
This output goes high when the PLL is frequency locked to
the input reference.
19
C2o
Clock 2.048MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s.
20
C4o
Clock 4.096MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s and
4.096Mb/s.
21
C19o
Clock 19.44MHz (CMOS Output).
This output is used in OC3/STS3 applications.
22
FLOCK
Fast Lock Mode (Input).
Set high to allow the PLL to quickly lock to the input reference (less
than 500 ms locking time).
24
IC
Internal Connection.
Tie low for normal operation.
25
C8o
Clock 8.192MHz (CMOS Output).
This output is used for ST-BUS operation at 8.192Mb/s.
26
C16o
Clock 16.384MHz (CMOS Output).
This output is used for ST-BUS operation with a
16.384MHz clock.
27
C6o
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
29
IM
Impairment Monitor (CMOS Output).
A logic high on this pin indicates that the Input
Impairment Monitor has automatically put the device into Freerun Mode.
30
IC
Internal Connection.
Tie high for normal operation.
32
NC
No Connection.
Leave open circuit
.
33,34,
42
IC
Internal Connection.
Tie low for normal operation.
36
MS
Mode/Control Select (Input).
This input determines the state (Normal or Freerun) of
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
37, 39
IC
Internal Connection.
Tie low for normal operation.
40
FS2
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four possible
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the REF input. See
Table 1.
41
FS1
Frequency Select 1 (Input).
See pin description for FS2.
44
TDO
Test Serial Data Out (CMOS Output).
JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
45
TDI
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
Test Reset (Input).
Asynchronously initializes the JTAG TAP controller by putting it in the Test-
Logic-Reset state.
46
TRST
47
TCK
Test Clock (Input).
Provides the clock to the JTAG test logic.
48
TMS
Test Mode Select (Input).
JTAG signal that controls the state transitions of the TAP controller.
Pin Description (continued)
Pin #
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9042B | () |
| MT9042C | Multitrunk System Synchronizer(多中繼系統(tǒng)同步裝置) |
| MT9043 | T1/E1 System Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90401 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| MT90401AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH System Synchronizer |
| MT90401AB1 | 制造商:Microsemi Corporation 功能描述:FRAMER SDH/SONET 3.3V 80LQFP EP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER SONET/SDH 80LQFP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER SONET/SDH 80LQFP |
| MT9040AN | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Synchronizer |
| MT9040AN1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Rail/Tube |
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