參數(shù)資料
型號： MT90401AB1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： SONET/SDH System Synchronizer
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80
文件頁數(shù)： 23/38頁
文件大?。?/td> 650K
代理商： MT90401AB1
MT90401
Data Sheet
23
Zarlink Semiconductor Inc.
3.13 Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
1. initial input to output phase difference
2. initial input to output frequency difference
3. synchronizer loop filter
4. synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT90401 loop filter
and limiter were optimized to meet the GR-253-CORE, GR-1244-CORE, and G-813 jitter transfer and phase slope
requirements.
4.0 MT90401 and Network Specifications
The MT90401 meets all applicable PLL requirements for the following specifications.
1. Telcordia GR-1244-CORE December 2000 for Stratum 3, SONET Minimum Clock (SMC), Stratum 4 Enhanced
and Stratum 4
2. Telcordia GR-253-CORE September 2000 for SONET Internal Clocks
3. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4
4. ANSI T1.105.09-1996 for SONET Minimum Clocks (SMCs)
5. ITU-T G.813 August 1996 for Option1 and Option 2 clocks (with external jitter attenuator)
5.0 Applications
This section contains MT90401 application specific details for Master clock operation, LVDS output drivers setup,
microport functionality and output clock phase adjustment.
5.1 Master Clock
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source
at the C20i input pin.
Another consideration in determining the accuracy of the master timing source is the desired capture range. The
sum of the accuracy of the master timing source and the capture range of the MT90401 will always equal 52 ppm.
For example, if the master timing source is
±
20 ppm, then the capture range will be
±
32 ppm.
5.2 TIE Correction (using PCCi)
When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will
prevent unwanted accumulated phase change between the input and output.
For example, we can estimate phase accumulation for a case when ten Normal to Holdover to Normal sequential
mode changes occur, with each Holdover entered for 2 s with TIE enabled. Each mode change could account for a
phase shift as large as 250 ns. Thus, the accumulated phase could be as large as 2.9 us, and, the overall MTIE
could be as large as 2.9 us.
相關(guān)PDF資料
PDF描述
MT9040 T1/E1 Synchronizer
MT9040AN T1/E1 Synchronizer
MT9043 T1/E1 System Synchronizer
MT9043AN T1/E1 System Synchronizer
MT9043AN48PINSSOP T1/E1 System Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9040AN 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Synchronizer
MT9040AN1 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Rail/Tube
MT9040ANR1 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Tape and Reel
MT9041 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multiple Output Trunk PLL
MT9041AP 制造商:Microsemi Corporation 功能描述:WAN/PLL 制造商:Zarlink Semiconductor Inc 功能描述:WAN/PLL
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*