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參數(shù)資料
| 型號(hào)： | MT90401AB1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH System Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁(yè)數(shù)： | 1/38頁(yè) |
| 文件大?。?/td> | 650K |
| 代理商： | MT90401AB1 |
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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Meets requirements of GR-253-CORE for SONET
Stratum 3 and SONET minimum clock
Meets requirements of GR-1244-CORE Stratum 3
Meets requirements of G.813 Option 1 and Option
2 for SDH Equipment Clocks (SEC) with external
jitter attenuator
Provides OC-3/STM-1, DS3, E3, 19.44 MHz,
DS2, E1, T1, 8 kHz and ST-BUS clock outputs
Accepts reference inputs from two independent
sources
Selectable 1.544 MHz, 2.048 MHz, 19.44 MHz or
8kHz input reference frequencies
Holdover accuracy of 0.02 ppm
Adjustable output clock phase supporting master-
slave arrangements
Hardware or microprocessor control (8 bit
microprocessor interface)
3.3 V supply
JTAG boundary scan
Applications
SONET/SDH Add/Drop multiplexers
SONET/SDH uplinks
Integrated access devices
ATM edge switches
Description
The MT90401 is a digital phase locked loop (DPLL)
that is designed to synchronize SDH (Synchronous
Digital Hierarchy) and SONET (Synchronous Optical
Network) networking equipment. The MT90401 is used
to ensure that the timing of outgoing signals remains
within the limits specified by Telcordia, ANSI and the
ITU during normal operation and in the presence of
disturbances on the incoming synchronization signals.
January 2005
Ordering Information
MT90401AB
MT90401AB1
80 Pin LQFP
80 Pin LQFP*
*Pb Free Matte Tin
-40
°
C to +85
°
C
Trays
Trays
MT90401
SONET/SDH System Synchronizer
Data Sheet
Figure 1 - Functional Block Diagram
Virtual
Reference
Selected
Refer-
ence
IEEE
1149.1a
Reference
Select
Feedback
TIE
Corrector
Enable
Control State Machine
DPLL
State
Select
State
Select
Frequency
Select
MUX
Input
Impairment
Monitor
Output
Interface
Circuit
Reference
Select
MUX
TIE
Corrector
Circuit
MS1 MS2
FS1
FS2
TCK
TDI
TMS
TRST
SEC
RST
RSEL
VDD
VSS
TCLR
C1.5o
C2o
C4o
C6o
C19o
C8o
C16o
C44/C34
F0o
F8o
F16o
TDO
HOLDOVER
FLOCK
PCCi
LOCK
Reference
Monitor
Prioor
Secoor
D0/D7 A0/A6 CS,DS,R/W
C155P/N
C20i
Master Clock
PRI
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PDF描述 |
|---|---|
| MT9040 | T1/E1 Synchronizer |
| MT9040AN | T1/E1 Synchronizer |
| MT9043 | T1/E1 System Synchronizer |
| MT9043AN | T1/E1 System Synchronizer |
| MT9043AN48PINSSOP | T1/E1 System Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9040AN | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Synchronizer |
| MT9040AN1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Rail/Tube |
| MT9040ANR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Tape and Reel |
| MT9041 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multiple Output Trunk PLL |
| MT9041AP | 制造商:Microsemi Corporation 功能描述:WAN/PLL 制造商:Zarlink Semiconductor Inc 功能描述:WAN/PLL |
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