參數(shù)資料
型號(hào)： MT8LSDT3264AGI-133
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM MODULE
中文描述： 同步DRAM模塊
文件頁數(shù)： 17/24頁
文件大?。?/td> 614K
代理商： MT8LSDT3264AGI-133
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
17
2002, Micron Technology Inc.
Notes
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
, V
DDQ
= +3.3V;
T
A
= 25°C; pin under test biased at 1.4; f = 1 MHz.
3. IDD is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured (Com-
mercial Temperature: 0°C T
A
+70°C and Indus-
trial Temperature: -40°C
6. An initial pause of 100μs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (V
DD
and V
DDQ
must be powered up simultaneously. V
SS
and V
SSQ
must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
7. AC characteristics assume
t
T = 1ns.
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between
V
IH
and V
IL
(or between V
IL
and V
IH
) in a mono-
tonic manner.
9. Outputs measured at 1.5V with equivalent load:
+85 C).
10.
t
HZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
V
OH
or V
OL
. The last valid data element will meet
t
OH before going High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
=
3V, with timing referenced to 1.5V crossover point.
If the input transition time is longer than 1ns,
then the timing is referenced at V
IL
(MAX) and V
IH
(MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no
more than once every two clocks and are other-
wise at valid V
IH
or V
IL
levels.
13. I
DD
specifications are tested after the device is
properly initialized.
14. Timing actually specified by
t
CKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
15. Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle
rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The I
DD
current will increase or decrease propor-
tionally according to the amount of frequency
alteration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on
t
CK = 10ns for -10E, and
t
CK = 7.5ns for -
133 and -13E.
22. V
IH
overshoot: V
IH
(MAX) = V
DDQ
+ 2V for a pulse
width
3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
under-
shoot: V
IL
(MIN) = -2V for a pulse width 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
t
WR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (
t
RP) begins 7ns for -13E; 7.5ns for -133
and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
and is guaranteed by design.
28. Parameter guaranteed by design.
29. The value of
t
RAS used in -13E speed grade mod-
ule SPDs is calculated from
t
RC -
t
RP = 45ns.
30. For -10E, CL= 2 and
t
CK = 10ns; for -133, CL = 3
and
t
CK = 7.5ns; for -13E, CL = 2 and
t
CK = 7.5ns.
31. CKE is HIGH during refresh command period
t
RFC (MIN) else CKE is LOW. The I
DD
6 limit is
actually a nominal value and does not result in a
fail value.
32. Leakage number reflects the worst-case leakage
possible through the module pin, not what each
memory device contributes.
33. Leakage number reflects the worst-case leakage
possible through the module pin, not what each
memory device contributes.
t
AC for -133/-13E at CL = 3 with no load is 4.6ns
Q
50pF
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