參數(shù)資料
型號(hào): MT8977AP
廠商: Mitel Networks Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 2/26頁
文件大?。?/td> 344K
代理商: MT8977AP
MT8977
ISO-CMOS
Preliminary Information
4-100
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
DIP
PLCC
1
2
TxA
Transmit A Output.
Unipolar output that can be used in conjunction with TxB and
external line driver circuitry to generate the bipolar DS1 signal.
2
3
TxB
Transmit B Output.
Unipolar output that can be used in conjunction with TxA
and external line driver circuitry to generate the bipolar DS1 signal.
3
5
DSTo
Data ST-BUS Output.
A 2048 kbit/s serial output stream which contains the 24
PCM or data channels received from the DS1 line.
4
4
NC
No Connection.
5
9
RxA
Receive A Complementary Input.
Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with
RxB, detects bipolar violations in the received signal.
6
10
RxB
Receive B Complementary Input.
Accepts a unipolar split phase signal
decoded externally from the received DS1 bipolar signal. This input, in
conjunction with RxA, detects bipolar violations in the received signal.
7
11
RxD
Receive Data Input.
Unipolar RZ data signal decoded from the received DS1
signal. Generally the signals input at RxA and RxB are combined externally with a
NAND gate and the resulting composite signal is input at this pin.
8
13
CSTi1
Control ST-BUS Input #1.
A 2048 kbit/s serial control stream which carries 24
per-channel control words.
9
14
TxFDL
Transmit Facility Data Link (Input).
A 4 kHz serial input stream that is
multiplexed into the FDL position in the ESF mode, or the F
S
pattern when in SLC-
96 mode. It is clocked in on the rising edge of TxFDLClk.
10
16
TxFDLClk
Transmit Facility Data Link Clock (Output).
A 4 kHz clock used to clock in the
FDL data.
11
NC
No connection.
T
T
N
D
V
I
N
F
N
E
C1.5i
RxSF
TxSF
NC
NC
C2i
NC
NC
NC
NC
RxFDL
NC
NC
RxA
RxB
RxD
NC
CSTi1
TxFDL
NC
TxFDLClk
NC
V
C
E
N
V
D
R
C
N
X
X
V
28 PIN CERDIP/PDIP
TxA
TxB
DSTo
NC
RxA
RxB
RxD
CSTi1
TxFDL
TxFDLClk
NC
CSTi0
E8Ko
VSS
VDD
IC
F0i
E1.5i
C1.5i
RxSF
TxSF
C2i
RxFDL
DSTi
RxFDLClk
CSTo
XSt
XCtl
1
6 5 4 3 2
7
8
9
10
11
12
13
14
15
16
17
44 434241 40
39
38
37
36
35
34
33
32
31
30
29
23
1819 202122
24252627 28
44 PIN PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
相關(guān)PDF資料
PDF描述
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