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參數資料
| 型號： | MT8972BP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| 中文描述： | ISO2 -意法半導體的CMOS總線⑩家庭數字用戶接口電路的數字網絡接口電路 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 390K |
| 代理商： | MT8972BP |
MT8971B/72B
9-120
Applications
Typical connection diagrams are shown in Figures
13 and 14 for the DN mode as a MASTER and
SLAVE, respectively. L
OUT
is connected to the
coupling transformer through a resistor R2 and
capacitors C2
and C2’
characteristic impedance. Suggested values of R2,
C2 and C2’ for 80 and 160 kbit/s operation are
provided in Figures 13 and 14. Overvoltage
protection is provided by R1, D1 and D2. C1 is
present to properly bias the received line signal for
the L
IN
input. A 2:1 coupling transformer is used to
couple to the line with a secondary center tap for
optional phantom power feed. Varistors have been
shown for surge protection against such things as
lightning strikes.
to match the line
If the scramblers power up with all zeros in them,
they are not capable of randomizing all-zeros data
sequence. This increases the correlation between
the transmit and receive data which may cause loss
of convergence in the echo canceller and high bit
error rates.
In DN mode the insertion of the SYNC pattern will
provide enough pseudo-random activity to maintain
convergence. In MOD mode the SYNC pattern is not
inserted. For this reason, at least one ”1” must be fed
into the DNIC on power up to ensure that the
scramblers will randomize any subsequent all-zeros
sequence.
Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s
Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s
DV Port ST-BUS
CD Port ST-BUS
Master Clocks
Mode Select
Lines
{
{
{
+5V
0.33
μ
F
0.33
μ
F
DSTi
DSTo
CDSTi
CDSTo
F0
C4
MS0
MS1
MS2
V
Ref
V
Bias
L
OUT
L
IN
OSC1
OSC2
F0o
NC
D.C. coupled,
Frequency locked
10.24 MHz clock.
Refer to AC Electrical
Characteristics
Clock Timing
R2 = 390
R1 = 47
C2’ = 1.5 nF
C2 = 22 nF
+5V
D1 = D2 = MUR405
D2
2 : 1
1.0
μ
F
Line Feed
Voltage
For 80 kbit/s: C2’ = 3.3 nF
C1 = 0.33
μ
F
68 Volts
(Typ)
2.5 Joules
0.02 Watt
Note:
Low leakage diodes (1 & 2) are required so
that the DC voltage at L
IN
≈
V
Bias
To Next DNIC
MT8971B/72B
DN Mode
DV Port ST-BUS
CD Port ST-BUS
Master Clocks
Mode Select
Lines
+5V
0.33
μ
F
0.33
μ
F
DSTi
DSTo
CDSTi
CDSTo
F0
C4
MS0
MS1
MS2
V
Ref
V
Bias
L
OUT
L
IN
OSC1
OSC2
R2 = 390
R1 = 47
C2’ = 1.5 nF
C2 = 22 nF
+5V
D1 = D2 = MUR405
D2
2:1
{
{
{
1.0
μ
F
For 80 kbit/s: C2’ = 3.3 nF
C1 = 0.33
μ
F
68 Volts
(Typ)
2.5 Joules
0.02 Watt
Note:
Low leakage diodes (1 & 2) are required so
that the DC voltage at L
IN
≈
V
Bias
10.24 MHz XTAL
C3=33pF=C4
Supply
MT8971B/72B
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