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參數(shù)資料
| 型號(hào)： | MT8950 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
| 中文描述： | 異意法半導(dǎo)體的CMOS總線⑩系列數(shù)據(jù)編解碼器 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 223K |
| 代理商： | MT8950 |
MT8950
ISO-CMOS
6-16
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1:
R
L
=10K
to V
DD
, C
L
=150 pF to V
SS
DC Electrical Characteristics
V
DD
=5.0V±10%; V
SS
=0V; T
A
=0
o
C to 70
o
C - Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
O
U
T
P
U
T
S
Output LOW voltage
V
OL
V
OH
I
OL
0.05
V
| I
O
|< 1.0 μA V
DD
= 5V
| I
O
|< 1.0 μA V
DD
= 5V
V
OL
=0.4V
2
Output HIGH Voltage
4.95
V
3
Output LOW Current (On all
outputs except DSTo)
2.2
2.8
mA
4
Output HIGH Current (On all
outputs except DSTo)
I
OH
-3.5
-4.2
mA
V
OH
=2.4V
5
Output LOW Current (On
DSTo output)
I
OL
8.9
11.1
mA
V
OL
=0.4V
6
Output HIGH Current (On
DSTo output)
I
OH
-14.0
-16.8
mA
V
OH
=2.4V
7
Output Leakage Current
I
OZ
±1
±10
μA
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
C2i Clock Frequency
f
CK
t
CR
t
CF
2.028
2.048
2.068
MHz
2
C2i Clock Rise Time
50
ns
3
C2i Clock Fall Time
50
ns
4
Clock Duty Cycle (C2i & SCLK)
50
%
5
SCLK Clock Frequency
f
SCLK
t
SCLKR
t
SCLKF
t
ER
t
EF
t
ES
t
EH
t
OR
t
OF
t
PZH
t
PZL
t
PLH
t
PHL
t
IR
t
IF
t
ISH
t
ISL
t
IH
0
0.6
128
kHz
6
SCLK Clock Rise Time
50
ns
7
SCLK Clock Fall Time
50
ns
8
F1i and CA Rise Time
100
ns
9
F1i and CA Fall Time
100
ns
10
F1i and CA Setup Time
25
ns
11
F1i and CA Hold Time
-25
25
ns
12
DSTo Rise Time
100
ns
Note 1
13
DSTo Fall Time
100
ns
Note 1
14
Propagation Delay From Clock
(C2i) To Output (DSTo) enable.
ns
Note 1
15
Propagation Delay From Clock
(C2i) To Output (DSTo).
125
ns
Note 1
16
Input Rise Time (DSTi, CSTi)
100
ns
17
Input Fall Time (DSTi, CSTi)
100
ns
18
DSTi, CSTi Setup Time
0
ns
19
DSTi, CSTi Hold Time
90
ns
20
PRST Low Time
488
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8950AC | ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
| MT8952BC | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952BE | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952BP | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952BS | ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8950AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
| MT8952 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952B-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
| MT8952BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller |
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