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參數(shù)資料
| 型號： | MT8940AE |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL |
| 中文描述： | 異意法半導(dǎo)體的CMOS總線⑩家庭T1/CEPT數(shù)字集群鎖相環(huán) |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 299K |
| 代理商： | MT8940AE |
ISO-CMOS
MT8940
3-39
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output
AC Electrical Characteristics
-Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Ref. Figures 11&12)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
D
P
L
L
#2
C4b output delay (HIGH to
LOW) from C8Kb input/output
t
84H
-25
75
ns
Test load circuit 2 (Fig. 17)
on C8Kb.
2
C4b output clock period
t
P4o
t
W4oH
t
W4oL
t
rC4
t
fC4
240
282
ns
Test load circuit 1 (Fig. 17).
3
C4b output clock width (HIGH)
123
165
ns
4
C4b output clock width (LOW)
110
123
ns
5
C4b output clock rise time
10
ns
Test load circuit 1 (Fig. 17).
6
C4b clock output fall time
10
ns
Test load circuit 1 (Fig. 17).
7
Frame pulse output delay
(HIGH to LOW) from C4b
t
FPL
50
ns
Test load circuit 1 (Fig. 17).
8
Frame pulse output delay
(LOW to HIGH) from C4b
t
FPH
40
ns
Test load circuit 1 (Fig. 17).
9
Frame pulse (F0b) width
t
WFP
t
4oLH
t
4oHL
200
245
ns
10
C4o delay - LOW to HIGH
45
ns
11
C4o delay - HIGH to LOW
45
ns
12
C4b to C2o delay (LOW to
HIGH)
t
42LH
-10
+10
ns
13
C4b to C2o delay (HIGH to
LOW)
t
42HL
20
ns
14
C2o clock period
t
P2o
t
W2oH
t
W2oL
t
rC2
t
fC2
t
2oLH
t
2oHL
486
523
ns
Test load circuit 1 (Fig. 10).
15
C2o clock width (HIGH)
244
291
ns
16
C2o clock width (LOW)
233
244
ns
17
C2o clock rise time
10
ns
Test load circuit 1 (Fig. 10).
18
C2o clock fall time
10
ns
Test load circuit 1 (Fig. 10).
19
C2o delay - LOW to HIGH
ns
20
C2o delay - HIGH to LOW
-5
30
ns
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
C4b
F0b
C8Kb
as
Output
C8Kb
as
Input
t
84H
t
W4oH
t
P4o
t
FPL
t
FPH
t
W4oL
相關(guān)PDF資料 |
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|---|---|
| MT8941B | Advanced T1/CEPT Digital Trunk PLL(先進(jìn)的T1/CEPT數(shù)字中繼鎖相環(huán)) |
| MT8941B | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8950 | ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8941 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
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