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參數(shù)資料
| 型號(hào)： | MT8940AC |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/CEPT Digital Trunk PLL |
| 中文描述： | T1/CEPT數(shù)字集群鎖相環(huán) |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 299K |
| 代理商： | MT8940AC |
MT8940
ISO-CMOS
3-40
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 13 - F0b from DPLL #2 is Looped Back as Input to DPLL #1 (T1 Line synchronized to ST-BUS)
Timing is over recommended temperature & power supply voltages
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 14 - Master Clock Inputs
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Ref. Figure 13)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
CV/CVb (1.544 MHz) Setup time
t
S15
t
H15
25
ns
2
CV/CVb (1.544 MHz) Hold time
110
ns
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Ref. Figure 14)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
C
L
O
C
K
S
Master clocks input rise time
t
r
t
f
10
ns
2
Master clocks input fall time
10
ns
3
Master clock period
(12.355MHz)
t
P12
80.930
80.938
80.946
ns
For DPLL #1, while operating to
provide the T1 clock signal.
4
Master clock period
(16.388MHz)
t
P16
61.018
61.020
61.022
ns
For DPLL #2, while operating to
provide the CEPT and ST-BUS
timing signals.
5
Duty Cycle of master clocks
45
50
55
%
6
Lock-in Range (For each PLL)
-1.5
+1.04
Hz
With the Master clocks as shown
above.
F0b
C2o
CV
CVb
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
t
S15
t
H15
Boundary between ST-BUS channel 2 bit 4 and
channel 2 bit 3
20 CYCLES
t
H15
t
S15
Master clock
inputs
2.4 V
1.5 V
0.4 V
t
r
t
f
t
P12
or t
P16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8940AE | ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL |
| MT8941B | Advanced T1/CEPT Digital Trunk PLL(先進(jìn)的T1/CEPT數(shù)字中繼鎖相環(huán)) |
| MT8941B | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BE | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8940AE | 制造商:MITEL 功能描述: |
| MT8941 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| MT8941B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
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