參數(shù)資料
型號(hào): MT8931C
廠商: Mitel Networks Corporation
英文描述: Subscriber Network Interface Circuit(用戶網(wǎng)絡(luò)接口電路(提供點(diǎn)到點(diǎn)或點(diǎn)到多點(diǎn)數(shù)字傳送))
中文描述: 用戶網(wǎng)絡(luò)接口電路(用戶網(wǎng)絡(luò)接口電路(提供點(diǎn)到點(diǎn)或點(diǎn)到多點(diǎn)數(shù)字傳送))
文件頁(yè)數(shù): 9/40頁(yè)
文件大?。?/td> 309K
代理商: MT8931C
MT8931C
9-79
with zeros in the B and D-channel and the
activation bit (A-bit) set to zero.
4) As soon as the TE synchronizes to Info2, it
responds with a valid S-Bus frame with data in
the B1, B2 and D-channel (Info3).
5) The NT will then transmit a valid frame with data
in the B1, B2 and D-channel. It will also set the
activation
bit
(A)
synchronization to Info3 is achieved.
to
binary
one
once
If the NT wishes to initiate the activation, steps 2 and
3 are ignored and the NT starts sending Info2. To
initiate a deactivation, either end begins to send
Info0 (Idle line).
D-channel Priority Mechanism
The SNIC contains a hardware priority mechanism
for D-channel contention resolution. All TEs
connected in a point-to-multipoint configuration are
allocated
the
D-channel
approach.
Allocation
accomplished by monitoring the D-echo channel
(E-bit) and incrementing the D-channel priority
counter with every consecutive one echoed back in
using
of
a
D-channel
systematic
the
is
the E bit. Any zero found on the D-echo channel will
reset the priority counter.
There are two classes of priority within the SNIC,
one user accessible and the other being strictly
internal. The user accessible priority selects the
class of operation and has precedence over the
internal priority. The latter (internal priority), will
select the level of priority within each class (i.e., the
internal priority is a subsection of the user accessible
priority). User accessible priority selects the
terminal count as 8/9 or 10/11 consecutive ones on
the E-bit (8 being high priority while 10 being low
priority). The internal priority selects the terminal
between 8 or 9 for high class and 10 or 11 for low
class. The first terminal equipment to attain the E-bit
priority count will immediately take control of the
D-channel by sending the opening flag. If more than
one terminal has the same priority, all but one of
them will eventually detect a collision. The TEs that
detect a collision will immediately stop trans-mitting
on the D-channel, generate an interrupt through the
Dcoll bit, reset the DCack bit on the next frame
pulse, and restart the counting process. The
remainder of the packet in the Tx FIFO is ignored.
Figure 8 - Point-to-Point Configuration
Figure 9 - Short Passive Bus Configuration, up to 8 TEs can be supported
Figure 10 - Extended Passive Bus Configuration, up to 8 TEs can be supported
NT
TE
T
R
T
R
0 - 1 Km
NT is operating in adaptive timing
TR is the line termination resistor = 100
NT
TE
T
R
T
R
TE
TE
TE
TE
TE
TE
TE
100 m for 75
impedance cable and 200 m for 150
impedance cable
100 - 200 m
NT is operating in fixed timing
TR is the line termination resistor = 100
0 - 10 m
NT is operating in adaptive timing
TR is the line termination resistor = 100
TE
TE
TE
TE
TE
TE
TE
0 - 10 m
0-500 m
0-50 m
NT
T
R
T
R
TE
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