參數(shù)資料
型號(hào): MT8931B
廠商: Mitel Networks Corporation
英文描述: ()
中文描述: ()
文件頁(yè)數(shù): 19/29頁(yè)
文件大小: 277K
代理商: MT8931B
Application Note
MSAN-141
A-219
Figure 20 - Transmitter Output Pulse Template
V=100%
50%
7%
0%
10%
10%
5%
5%
10%
Nominal Pulse
5.73
μ
s
4.17
μ
s
(5.21 - 1.04)
5.21
μ
s
4.69
μ
s
(5.21 - 0.52)
6.25
μ
s
(5.21 + 1.04)
10.42
μ
s
(5.21 + 5.21)
minimum threshold set to 16 dB below nominal pulse
amplitude. This minimum threshold on the input
circuit is required to maintain the active region of the
input signal well above the noise and crosstalk
levels.
5.3
PLL and Jitter
The SNIC has self-contained clock recovery using an
on chip analog phase-locked loop. Incorporated in
the Phase-Locked Loop (PLL) is a voltage controlled
oscillator which allows the SNIC to function without
an external crystal. The PLL has both a phase and
frequency detection circuit which accelerates phase
acquisition. The extracted clock is presented on the
C4b pin with a nominal frequency of 4.096 MHz. If
the TE mode of the MT8930B is selected by tying pin
CK/NT low, then the frequency of the VCO will
deviate from its nominal value in the absence of a
line signal. For TE applications requiring a stable and
constant VCO frequency at all times, the CK/NT pin
of the MT8930B should be connected to a 4.096
MHz clock. This clock input will still configure the
device in TE mode while serving to train the PLL in
the absence of a line signal on the S/T bus. Note that
the MT8931B, on the other hand, requires a clock
input or a crystal to be connected to pin XTAL1/NT in
order to select TE mode. Therefore, the VCO
frequency is always centered at the proper value.
Under all conditions the TE will phase-lock to the
INFO2 signal within 50 ms. An inherent advantage of
Figure 21 - Receiver Circuit
1: 2
LRx
V
Bias
Lowpass
Filter
Highpass
Filter
Peak
Detector
Positive
Peak
Detector
Negative
Data
Recovery
Circuit
RPos
RNeg
SNIC
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