參數(shù)資料
型號(hào): MT8885
廠商: Mitel Networks Corporation
英文描述: Integrated DTMF Transceiver with Power Down and Adaptive Micro Interface(雙音多頻信號(hào)(DTMF)收發(fā)器(帶電源關(guān)閉和自適應(yīng)微接口))
中文描述: 集成雙音多頻收發(fā)器的斷電和自適應(yīng)微型接口(雙音多頻信號(hào)(DTMF)的收發(fā)器(帶電源關(guān)閉和自適應(yīng)微接口))
文件頁(yè)數(shù): 9/25頁(yè)
文件大?。?/td> 190K
代理商: MT8885
Preliminary Information
MT8885
4-59
DS/RD on the falling edge of CS. For Motorola bus
timing DS/RD must be low on the falling edge of CS.
Figure
12(a)
shows
the
MC68HC11 Motorola processor to the MT8885
DTMF transceiver.
connection
of
the
Figures 17 and 18 are the timing diagrams for Intel
micro-controllers with multiplexed address and data
buses. The MT8885 latches in the state of DS/RD on
the falling edge of CS. When DS/RD is high, Intel
processor operation is selected. By NANDing the
address latch enable (ALE) output with the high-byte
address (P2) decode output, CS can be generated.
Figure 12(b) shows the connection of these Intel
processors to the MT8885 transceiver.
NOTE:
The adaptive micro interface relies on high-
to-low
transition
on
microcontroller interface. This pin must not be tied
permanently low. Only one register access is allowed
on any CS assertion.
The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last valid
DTMF digit received. Data entered into the write-only
Transmit Data Register will determine which tone
pair is to be generated (see Table 1 for coding
details). Transceiver control is accomplished with two
control registers (see Tables 6 and 7), CRA and
CRB, which have the same address. A write
operation to CRB is executed by first setting the most
significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
CS
to
recognize
the
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 14). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
Table 3. Internal Register Functions
Table 4. CRA Bit Positions
Table 5. CRB Bit Positions
Motorola
Intel
RS0
R/W
WR
RD
FUNCTION
0
0
0
1
Write to Transmit
Data Register
0
1
1
0
Read from Receive
Data Register
1
0
0
1
Write to Control Register
1
1
1
0
Read from Status Register
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
b3
b2
b1
b0
C/R
S/D
RxEN
BURST
ENABLE
Figure 12 a) & b) - MT8885 Interface Connections for Various Intel and Motorola Micros
MT8885
MT8885
8031/8051/
8080/8085
A8-A15
AS
AD0-AD3
RW
CS
RS0
DS/RD
D0-D3
R/W/WR
E
A8-A15
ALE
P0
RD
WR
CS
D0-D3
RS0
DS/RD
R/W/WR
12 (b) Intel
12 (a) Motorola
MC68HC11
相關(guān)PDF資料
PDF描述
MT8888CE-1 Integrated DTMFTransceiver with Intel Micro Interface
MT8888CN-1 CB 3C 3#16S SKT RECP WALL
MT8888CS-1 Integrated DTMFTransceiver with Intel Micro Interface
MT8888C Integrated DTMFTransceiver with Intel Micro Interface
MT8888CC Integrated DTMFTransceiver with Intel Micro Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8885AE 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface
MT8885AE1 制造商:Microsemi Corporation 功能描述:DTMF TXRX 3.58MHZ CMOS 5V 24PDIP - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX DTMF 20PDIP 制造商:Microsemi Corporation 功能描述:IC TXRX DTMF 20PDIP
MT8885AN 制造商:Microsemi Corporation 功能描述:DTMF TXRX 3.58MHZ CMOS 5V 24SSOP - Rail/Tube
MT8885AN1 制造商:Microsemi Corporation 功能描述:DTMF TXRX 3.58MHZ CMOS 5V 24SSOP - Rail/Tube
MT8885ANR 制造商:Microsemi Corporation 功能描述: