參數(shù)資料
型號: MT8885
廠商: Mitel Networks Corporation
英文描述: Integrated DTMF Transceiver with Power Down and Adaptive Micro Interface(雙音多頻信號(DTMF)收發(fā)器(帶電源關(guān)閉和自適應(yīng)微接口))
中文描述: 集成雙音多頻收發(fā)器的斷電和自適應(yīng)微型接口(雙音多頻信號(DTMF)的收發(fā)器(帶電源關(guān)閉和自適應(yīng)微接口))
文件頁數(shù): 17/25頁
文件大?。?/td> 190K
代理商: MT8885
Preliminary Information
MT8885
4-67
Characteristics are over recommended operating conditions unless otherwise stated
Typical figures are at 25
°
C, V
DD
=5V, and for design aid only: not guaranteed and not subject to production testing
NOTES: 1)
dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2)
Digit sequence consists of all 16 DTMF tones.
3)
Tone duration=40 ms. Tone pause=40 ms.
4)
Nominal DTMF frequencies are used.
5)
Both tones in the composite signal have an equal amplitude.
6)
The tone pair is deviated by
1.5%
2 Hz.
7)
Bandwidth limited (3 kHz) Gaussian noise.
8)
The precise dial tone frequencies are 350 and 440 Hz (
±
2%).
9)
Guaranteed by design and characterization. Not subject to production testing.
10)
Referenced to the lowest amplitude tone in the DTMF signal.
11)
For guard time calculation purposes.
12)
Operation of microprocessor interface requires that t
CL
+ t
CH
1000ns
Figure 15 - Digital Signal Input Rise/Fall Times
AC Electrical Characteristics
- MPU Interface
- Voltages are with respect to ground (V
SS
), unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Conditions
1
RD/WR low pulse width
t
CL
200
400
ns
Figure 15, Note 12
t
CL
+ t
CH
1000ns
Figure 15, Note 12
t
CL
+ t
CH
1000ns
Figure 15
2
DS high pulse width
t
CH
200
400
ns
3
Rise and fall time all digital inputs
t
R,
t
F
t
RWS
t
RWH
t
AS
t
AH
t
DHR
t
DDR
t
DSW
t
DHW
t
CSS
t
CSH
t
RDS,
t
DSS
20
ns
4
R/W setup time
23
ns
Figures 16
5
R/W hold time
20
ns
Figures 16
6
Address setup time (RS0)
0
ns
Figures 16 - 18
7
Address hold time (RS0)
40
ns
Figures 16 - 18
8
Data hold time (read)
22
ns
Figures 16 - 17
9
DS/RD to valid data delay (read)
100
ns
Figures 16 - 17
10
Data setup time (write)
45
ns
Figures 16, 18
11
Data hold time (write)
10
ns
Figures 16, 18
12
Chip select setup time
45
ns
Figures 16 - 18
13
Chip select hold time
40
ns
Figures 16 - 18
14
DS/RD set up time prior to CS
assertion
20
ns
Figures 16, 17
t
R
All Digital Inputs
t
F
V
HM
V
LM
*V
HM
= 0.7V
DD
, V
LM
= 0.3V
DD
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