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參數(shù)資料
| 型號： | MT8880C |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated DTMF Transceiver(雙音多頻信號（DTMF）收發(fā)器（帶電話程序?yàn)V波器）) |
| 中文描述： | 集成雙音多頻收發(fā)器（雙音多頻信號（DTMF）的收發(fā)器（帶電話程序?yàn)V波器）） |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 188K |
| 代理商： | MT8880C |
MT8880C
ISO
2
-CMOS
4-34
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20 24 28
1
2
3
1
2
3
1
2
4
IN+
IN-
GS
Non-inverting op-amp input.
Inverting op-amp input.
Gain Select
. Gives access to output of front end differential amplifier for connection of
feedback resistor.
V
Ref
Reference Voltage
output, nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig. 13).
V
SS
Ground input (0V).
OSC1 DTMF clock/oscillator input.
OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
10 12 TONE
Tone
output (DTMF or single tone).
11 13
R/W
Read/Write
input. Controls the direction of data transfer to and from the MPU and the
transceiver registers. TTL compatible.
10 12 14
CS
Chip Select
, TTL input (CS=0 to select the chip).
11 13 15
RS0
Register Select
input. See register decode table. TTL compatible.
12 14 17
Φ
2
System Clock
input. TTL compatible.
N.B.
Φ
2 clock input need not be active when the
device is not being accessed.
13 15 18
IRQ/
CP
been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal
representative of the input signal applied at the input op-amp. The input signal must be within
the bandwidth limits of the call progress filter. See Figure 8.
14-
17
21
22
18 22 26
ESt
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
19 23 27 St/GT
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 28
V
DD
Positive power supply input (+5V typical).
8,9
16,
17
11,
16,
23-
25
4
5
6
7
4
5
6
7
6
7
8
9
8
9
Interrupt Request to MPU
(open drain output). Also, when call progress (CP) mode has
18-
19-
D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or
Φ
2 is low.
3,5,
10,
NC
No Connection.
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
Φ
2
RS0
20 PIN PLASTIC DIP/SOIC
28 PIN PLCC
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
G
NC
VRef
VSS
OSC1
OSC2
NC
NC
NC
NC
Φ
2
3
2
1
2
2
2
1
1
1
1
1
1
1
N
I
I
V
S
E
T
R
C
R
N
I
NC
NC
NC
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
Φ
2
RS0
24 PIN SSOP
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| MT8880CC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS Integrated DTMFTransceiver |
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| MT8880CE/CE-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated DTMFTransceiver |
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