
Application Note
MSAN-108
A-57
Figure 14 - Block Diagram of Mobile Radio Control System
MOBILE TRANSCEIVER
RECEIVER
FUNCTIONS
TRANSMITTER
FUNCTIONS
carrier
operated
squelch
mute
receive
audio
transmit
enable
microphone
offhook
transmit
audio
MT8870
DTMF
RECEIVER
MT5089
DTMF
GENERATOR
CONTROL LOGIC OR
SINGLE CHIP MICROPROCESSOR
USER I.D. CODE
STRAPS
KEYPAD
AND DISPLAY
Distributed Control Systems
There are many other applications which also fall
into the distributed communications/control class.
That is, several devices being controlled via a
common communications medium whether it be RF,
copper wire or optical fibres, etc.
Consider, for example, an existing pair of wires
circulating throughout a plant. By connecting DTMF
receivers at strategic points along this path one
could conceivably control the whole plant from a
single DTMF transmitter (Fig. 15). Each DTMF
receiver would monitor the common line until its
specific I.D. was received, at which time it would
transfer data to its functional control logic.
With some simple logic a circuit can be devised to
recognize a sequence of programmed DTMF code.
Figure 16 illustrates a method of detecting a
DTMF code sequence of arbitrary length, N. The
object is to compare N sequential 4-bit DTMF data
words to N preprogrammed 4-bit I.D. words.
Programming the I.D. code is accomplished by
applying the desired logic levels to the inputs of N 4-
bit bus buffers. This may be achieved with straps as
shown, dipswitches or thumbwheels. Pull-up
resistors should be applied to the buffer inputs.
Initially, after a RESET has occurred, Q
0
of the
presettable shift register is set logically high, the
remaining outputs are reset. This activates the first
bus buffer which applies its outputs to the Y inputs of
a 4-bit comparator.The ”LAST DIGIT“ latch is reset,
the ”ERROR-“ flip-flop and ”VALID DIGIT“ latch are
set. These three signals are ANDed indicating a ”no-
match“ condition. When a valid DTMF signal is
received its data appears at the comparators ”X“
inputs, a comparison occurs and the result appears
at the ”X=Y“ output. After 3.4
μ
S (typical) Std rises
indicating that the MT8870 output data is valid and
strobes ”X=Y“ into the ”VALID DIGIT“ latch. The shift
register advances one position which enables the
next bus buffer. If the result of the comparison was
true then the ”VALID DIGIT“ output is high. If all
digits of the sequence match then the high output
from the shift register “wraps around“ from Q
N-1
to
Q
0,
which strobes the ”LAST DIGIT“ latch high. This
activates the three input AND gate indicating a
”match” condition. If non-matching data is received
any time during the detection sequence the
”ERROR-“ flip-flop is reset which disables the AND
gate until a system ”RESET“ occurs. ”RESET“ may
be generated in a variety of ways depending on the