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參數(shù)資料
| 型號： | MT884 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 87K |
| 代理商： | MT884 |
MSAN-144
Application Note
A-234
Figure 3 - Logic Controller and DCE Interface
VDD
R1
C1
RX/CS
CX
A
RD
RELAY
Q
QM
U1A
U3A
U4A
VDD
VDD
R2
CD
D
CK
CL
Q
QF
U5A
U5B
VDD
C2
C3
TRANSMIT
(RS-232)
DCD
(RS-232)
DATA
PWDN
CD
MT8841
Notes:
1.
2.
3.
Decoupling not shown.
U1-4 powered from +5V.
U5 powered from
±
12V.
Components List:
U1
U2
U3
U4
U5
R1
R2
C1
C2, C3
74HC123, MMV Retriggerable Dual
74HC74, D Flip-Flop Dual
74HC00, NAND 2IP Quad
74HC04, Inverter Hex
MC1488, RS-232 Line Driver Quad
820k, 1/2W 1%, Resistor Metal
10k, 1/2W 1%, Resistor Metal
10
μ
, 63V 20%, Capacitor Electrolytic
330p, 50V 20%, Capacitor Ceramic
U2A
Normally, the device is powered down, but during
FSK signal reception, it is powered up. A discrete
logic solution is shown in Fig. 3 which provides the
relay
termination
(RELAY)
powerdown (PWDN) control signals during the
period between the first and second ringing bursts.
The above two logic signals are generated by four
integrated circuits (U1 to U4). Input signals to the
controller are from the ringing detector (RD), and
CNIC carrier detect (CD) outputs. The timing
diagram for the logic controller is shown in Fig. 4.
Since the relay termination is activated by the first
carrier detection following the ringing signal, the
circuit will also function correctly for distinctive
ringing, where two quick ringing bursts are followed
by the FSK.
and
the
MT8841
The start of a ringing burst is signalled by the falling
edge of the ring detector (RD) output. This triggers
the Monostable Multivibrator (MMV) which generates
an 8 second output pulse at QM that powers up the
CNIC. Shortly after the first ringing burst, the central
office (CO) sends the FSK signal. The CNIC detects
this and the carrier detect output (CD) goes low, this
activates the termination relay. The end of FSK
transmission is signalled with CD going to logic high.
This clocks the flip flop resulting in a logic low at the
QF output. This deactivates the termination relay
which cannot be re-activated until ringing is once
again detected followed by a carrier detect signal.
In the RS-232 DCE line driver (Fig. 3), serial data
(DATA) and the carrier detect signal (CD) from the
MT8841 are converted to RS-232 levels and
provided as outputs (TRANSMIT and DCD). These
may be directly connected to a DCE such as a
personal computer with appropriate software.
Micro-Controller Parallel Read
The CNIC micro-controller interface (Fig. 5) is a
symbolic
circuit
showing
performing both the logic functions of Fig. 3 and the
data handling. The CNIC provides serial data
(DATA), data clock (DCLK), and data ready (DR)
signals that can be used to easily convert data from
a serial stream to a parallel stream (see Fig. 1).
Conversion is accomplished by connecting the serial
data and clock lines to an external shift register like a
74HC164. When the data ready line alerts the
micro-controller with an interrupt, it reads the shift
register's 8-bit parallel output. Only the 8-bit
character information of the 10-bit word is converted,
since the DCLK remains high for both stop and start
bits. The data ready signal indicates the reception of
every 10-bit word sent from the Central Office.
a
micro-controller
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