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參數(shù)資料
| 型號(hào)： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 134/189頁 |
| 文件大?。?/td> | 4133K |
| 代理商： | MT80C51T-36D |
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66
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 11-10. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. When either OCR0A or
ICR0 is used for defining the TOP value, the OC0A or ICF0 flag is set accordingly at the same timer clock cycle as
the OCR0x Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to gener-
ate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNT0 and the OCR0x. Note that when using fixed TOP values, the unused bits are
masked to zero when any of the OCR0x Registers are written. As the third period shown in Figure 11-10 on page
66 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in
an unsymmetrical output. The reason for this can be found in the time of update of the OCR0x Register. Since the
OCR0x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling
slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP
value. When these two values differ the two slopes of the period will differ in length. The difference in length gives
the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when chang-
ing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no
differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins. Setting
the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by set-
ting the COM0x1:0 to three (See Table 11-4 on page 73). The actual OC0x value will only be visible on the port pin
if the data direction for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or
clearing) the OC0x Register at the compare match between OCR0x and TCNT0 when the counter increments, and
clearing (or setting) the OC0x Register at compare match between OCR0x and TCNT0 when the counter decre-
ments. The PWM frequency for the output when using phase correct PWM can be calculated by the following
equation:
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1
2
3
4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
f
OCnxPCPWM
f
clk_I/O
2N TOP
-----------------------------
=
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