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參數(shù)資料
| 型號： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 123/189頁 |
| 文件大小： | 4133K |
| 代理商： | MT80C51T-36D |
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56
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Count
Increment or decrement TCNT0 by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNT0 (set all bits to zero).
clk
T0
Timer/Counter clock.
TOP
Signalize that TCNT0 has reached maximum value.
BOTTOM
Signalize that TCNT0 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) containing the upper
eight bits of the counter, and Counter Low (TCNT0L) containing the lower eight bits. The TCNT0H Register can
only be indirectly accessed by the CPU. When the CPU does an access to the TCNT0H I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT0H value
when the TCNT0L is read, and TCNT0H is updated with the temporary register value when TCNT0L is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is
important to notice that there are special cases of writing to the TCNT0 Register when the counter is counting that
will give unpredictable results. The special cases are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clk
T0). The clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be
accessed by the CPU, independent of whether clk
T0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM03:0) located in
the Timer/Counter Control Registers A and B (TCCR0A and TCCR0B). There are close connections between how
the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0x. For more
details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 61.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM03:0 bits.
TOV0 can be used for generating a CPU interrupt.
11.5
Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-
stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via
the ICP0 pin. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal
applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 11-5 on page 57. The elements of the
block diagram that are not directly a part of the Input Capture unit are gray shaded. The lower case “n” in register
and bit names indicates the Timer/Counter number.
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