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參數(shù)資料
| 型號(hào)： | MT5C6405 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 16K x 4 SRAM SRAM MEMORY ARRAY |
| 中文描述： | 16K的× 4 SRAM的存儲(chǔ)器陣列 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | MT5C6405 |
SRAM
MT5C6405
Austin Semiconductor, Inc.
MT5C6405
Rev. 2.0 5/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS
(GND).
2.
-3V for pulse width < 20ns
3.
I
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
t
RC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
t
HZCE
, t
HZOE
and t
HZWE
are specified with CL = 5pF as
in Fig. 2. Transition is measured ±200mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
.
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
12. CE2 timing is the same as CE1\ timing. The waveform
is inverted.
8.
9.
t
RC = Read Cycle Time.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
123
123
123
123
1234
1234
1234
1234
DON’T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
123456123
123456123
123456123
123456123
123456789
123456789
123456789
123456789
DATA RETENTION MODE
V
DR
> 2V
4.5V
4.5V
V
DR
t
CDR
t
R
V
IH
V
IL
V
CC
CE\
SYM
MIN
MAX
UNITS
NOTES
V
CC
for Retention Data
V
DR
2
---
V
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
I
CCDR
1
mA
Chip Deselect to Data
Retention Time
Operation Recovery Time
t
CDR
0
---
ns
4
t
R
t
RC
ns
4, 11
+5V
Q
255
30pF
480
5 pF
+5V
Q
255
480
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