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參數(shù)資料
| 型號(hào)： | MT5C6405 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 16K x 4 SRAM SRAM MEMORY ARRAY |
| 中文描述： | 16K的× 4 SRAM的存儲(chǔ)器陣列 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | MT5C6405 |
SRAM
MT5C6405
Austin Semiconductor, Inc.
MT5C6405
Rev. 2.0 5/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
12
15
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
15
15
20
20
25
25
35
35
2
2
2
2
2
2
2
2
2
2
7
7
8
10
12
15
6, 7
0
0
0
0
0
12
6
15
7
20
8
25
10
35
15
0
0
0
0
8
6
7
8
10
15
6
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
12
10
10
0
0
10
7
0
2
0
15
12
12
0
0
12
8
0
2
0
20
15
15
0
0
15
10
0
2
0
25
20
20
0
0
20
12
0
2
0
35
25
25
0
0
25
15
0
2
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
6
7
8
10
15
6, 7
NOTES
DESCRIPTION
-12
SYMBOL
UNITS
-35
-25
-20
-15
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