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參數(shù)資料
| 型號： | MT5C2565 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 64K x 4 SRAM MEMORY ARRAY |
| 中文描述： | 64K的× 4的SRAM內(nèi)存陣列 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 122K |
| 代理商： | MT5C2565 |
SRAM
MT5C2565
Austin Semiconductor, Inc.
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS
(GND).
2.
-3V for pulse width < 20ns
3.
I
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
t
RC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
t
HZCE
, t
HZOE
and t
HZWE
are specified with CL = 5pF as
in Fig. 2. Transition is measured ±500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
and
t
HZOE
is less than t
LZOE
.
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. t
RC
= Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
8.
9.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
123
123
123
123
1234
1234
1234
1234
DON’T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
12345678
12345678
12345678
12345678
12345678
12345678
12345678
12345678
DATA RETENTION MODE
V
DR
> 2V
4.5V
4.5V
V
DR
t
CDR
t
R
V
IH
V
IL
V
CC
CE\
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
+5V
Q
255
30pF
480
5 pF
+5V
Q
255
480
SYM
MIN
MAX
UNITS
NOTES
VCC for Retention Data
V
DR
2
---
V
Data Retention Current
V
CC
= 2V
I
CCDR
1
mA
*
Chip Deselect to Data
Retention Time
Operation Recovery Time
t
CDR
0
---
ns
4
t
R
t
RC
ns
4, 11
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
*for -25 and slower only
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