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參數(shù)資料
| 型號： | MT5C1008LL |
| 廠商： | Austin Semiconductor, Inc |
| 元件分類： | SRAM |
| 英文描述： | 128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER |
| 中文描述： | 128K的× 8，配有雙芯片啟用超低功耗的SRAM |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 129K |
| 代理商： | MT5C1008LL |
S R A M
MT5C1008(LL)
Ultra Low Power
Austin Semiconductor, Inc.
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
AC TEST LOADS AND WAVEFORMS
CAPACITANCE
1
PARAMETER
CONDITIONS
SYM
C
IN
MAX
8
UNITS
pF
Input Capacitance (A0 - A16)
Input Capacitance (CE\, WE\, OE\)
C
CLK
10
pF
Output Capacitance
C
OUT
12
pF
TA = 25°C, f = 1MHz,
Vcc = 5.0V
DATA RETENTION CHARACTERISTICS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5.0V +10%)
PARAMETER
CONDITIONS
Vcc for Data Retention
0.2V, Vcc = V
DR
= 2.0V,
CE1\ > Vcc - 0.3V or CE2 < 0.3V,
V
IN
> Vcc - 0.3V or V
IN
< 0.3V
SYM
V
DR
MIN
2.0
MAX
UNITS
V
Data Retention Current
I
CCDR
150
μA
Chip Deselect to Data Retention Time
t
CDR
0
ns
Operation Recovery Time
t
R
200
μs
NOTES:
1. Tested initially and after any design or process changes that may effect these parameters.
DATA RETENTION WAVEFORM
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