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參數(shù)資料
| 型號： | MT58L64L36FT-7.5 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| 中文描述： | 2MB的：128K的× 18，64K的x 32/36流通過SYNCBURST的SRAM |
| 文件頁數(shù)： | 16/24頁 |
| 文件大小： | 488K |
| 代理商： | MT58L64L36FT-7.5 |
16
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65
–
Rev. 6/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
BYTE WRITE signals are
ignored when ADSP# is LOW.
ADSC# extends burst.
ADV# suspends burst.
DON
T CARE
UNDEFINED
NOTE:
1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for the x18 version;
or GW# HIGH and BWE#, BWa#-BWd# LOW for the x32 and x36 versions.
-6.8
-7.5
-8.5
-10
SYMBOL
t
DS
t
CES
t
AH
t
ADSH
t
AAH
t
WH
t
DH
t
CEH
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.8
2.0
2.0
1.8
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
WRITE TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
SYMBOL
t
KC
f
KF
t
KH
t
KL
t
OEHZ
t
AS
t
ADSS
t
AAS
t
WS
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
8.0
8.8
10.0
125
113
1.8
1.9
1.9
1.8
1.9
1.9
3.8
4.2
1.8
2.0
2.0
1.8
2.0
2.0
1.8
2.0
2.0
1.8
2.0
2.0
15
ns
100
66
MHz
ns
ns
ns
ns
ns
ns
ns
4.0
4.0
5.0
5.0
2.5
2.5
2.5
2.5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT58L32L32D | 32K x 32,3.3V I/O, Pipelined, DCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L32L36D | 32K x 36,3.3V I/O, Pipelined, DCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L512Y32D | 16Mb SYNCBURST⑩ SRAM |
| MT58L64L18F | 64K x 18, 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM) |
| MT58L32L32F | 32K x 32， 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L64L36FT-8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L64L36FT-8.5 | 制造商:Cypress Semiconductor 功能描述: |
| MT58L64L36FT-8.5A | 制造商:Micron Technology Inc 功能描述: |
| MT58L64L36PT-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L64L36PT-10TR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Micron Technology Inc 功能描述: |
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