參數(shù)資料
型號: MT58L64L32P
廠商: Micron Technology, Inc.
英文描述: 64K x 32,Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
中文描述: 64K的× 32,流水線,SCD的SyncBurst的SRAM(處理器,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
文件頁數(shù): 6/25頁
文件大?。?/td> 487K
代理商: MT58L64L32P
6
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18
85
x32/x36
85
SYMBOL
ADSC#
TYPE
Input
DESCRIPTION
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
Mode: This input selects the burst sequence. A LOW on this pin
selects “l(fā)inear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with
Output DQa pins; Byte “b” is associated with DQb pins. For the x32 and x36
versions, Byte “a” is associated with DQa pins; Byte “b” is
associated with DQb pins; Byte “c” is associated with DQc pins;
Byte “d” is associated with DQd pins. Input data must meet setup
and hold times around the rising edge of CLK.
31
31
MODE
Input
64
64
ZZ
Input
(a)
58, 59,
62, 63, 68, 69, 56-59, 62, 63
72, 73
(b)
8, 9, 12,
13, 18, 19, 22, 72-75, 78, 79
23
(a)
52, 53,
DQa
(b)
68, 69,
DQb
(c)
2, 3, 6-9,
12, 13
(d)
18, 19,
22-25, 28, 29
51
80
1
30
DQc
DQd
74
24
NC/
DQPa
NC/
DQPb
NC
/DQPc
NC/
DQPd
V
DD
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these pins are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Supply Power Supply:
See DC Electrical Characteristics and Operating
Conditions for range.
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
Supply Ground:
GND.
14, 15, 41, 65, 14, 15, 41, 65,
91
4, 11, 20, 27, 4, 11, 20, 27,
54, 61, 70, 77 54, 61, 70, 77
5, 10, 17, 21, 5, 10, 17, 21,
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
38, 39, 42, 43 38, 39, 42, 43
91
V
DD
Q
V
SS
DNU
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
1-3, 6, 7, 16,
25, 28-30,
51-53, 56, 57,
66, 75, 78, 79,
95, 96
50
16, 66
NC
50
NC/
SA
No Connect: This pin is reserved for address expansion.
相關(guān)PDF資料
PDF描述
MT58L64V32P 64K x 32,Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
MT58L64L36P 64K x 36,Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
MT58L64V36P 64K x 36,Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
MT58L128L32D1 128K x 32,3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb,3.3V輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
MT58L128L36D1 128K x 36,3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb,3.3V輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT58L64L32PT-10 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
MT58L64L32PT-10 TR 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V
MT58L64L32PT-10TR 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
MT58L64L32PT-6 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
MT58L64L32PT-6 TR 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V