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參數(shù)資料
| 型號： | MT58L512L18DT-10IT |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 5 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026BHA, TQFP-100 |
| 文件頁數(shù)： | 7/31頁 |
| 文件大?。?/td> | 613K |
| 代理商： | MT58L512L18DT-10IT |
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8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18D_C.p65 – Rev. 6/01
2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
BGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
4A
ADSP#
Input
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to
be registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but
dependent upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is
HIGH. Power-down state is entered if CE2 is LOW or CE2# is
HIGH.
4B
ADSC#
Input
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to
be registered. A READ or WRITE is performed using the new
address if CE# is LOW. ADSC# is also used to place the chip into
power-down state when CE# is HIGH.
3R
MODE
Input
Mode: This input selects the burst sequence. A LOW on this input
selects “l(fā)inear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is
operating.
(a) 6F, 6H, 6L,
(a) 6K, 6L,
DQa
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa’s; Byte “b”
6N, 7E, 7G,
6M, 6N, 7K,
Output is DQb’s. For the x32 and x36 versions, Byte “a” is DQa’s;
7K, 7P
7L, 7N, 7P
Byte “b” is DQb’s; Byte “c” is DQc’s; Byte “d” is DQd’s. Input
(b) 1D, 1H,
(b) 6E, 6F,
DQb
data must meet setup and hold times around the rising edge of
1L, 1N, 2E,
6G, 6H, 7D,
CLK.
2G, 2K, 2M
7E, 7G, 7H
(c) 1D, 1E,
DQc
1G, 1H, 2E,
2F, 2G, 2H
(d) 1K, 1L,
DQd
1N, 1P, 2K,
2L, 2M, 2N
6D
6P
NF/DQPa
NF/
No Function/Parity Data I/Os: On the x32 version, these are No
2P
6D
NF/DQPb
I/O
Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte
–
2D
NF/DQPc
“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;
–
2P
NF/DQPd
Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity
is DQPd.
2J, 4C, 4J,
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
4R, 5R, 6J
Conditions for range.
1A, 1F, 1J,
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
and
1M, 1U, 7A,
Operating Conditions for range.
7F, 7J, 7M,
7U
3D, 3E, 3F,
VSS
Supply Ground: GND.
3H, 3K, 3L,
3H, 3K, 3M,
3M, 3N, 3P,
3N, 3P, 5D,
5D, 5E, 5F,
5E, 5F, 5H,
5G, 5H, 5K,
5K, 5M, 5N,
5M, 5N, 5P
5P
(continued on next page)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L512L18DT-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18F | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L512L18FF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FF-10IT | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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