參數(shù)資料
型號(hào)： MT58L512L18DS-7.5IT
元件分類(lèi)： SRAM
英文描述： 512K X 18 CACHE SRAM, 4 ns, PQFP100
封裝： PLASTIC, MS-026BHA, TQFP-100
文件頁(yè)數(shù)： 19/31頁(yè)
文件大小： 613K
代理商： MT58L512L18DS-7.5IT
26
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18D_C.p65 – Rev. 6/01
2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are ignored for first cycle when
ADSP# initiates burst.
ADSC# extends burst.
ADV# suspends burst.
DON’T CARE
UNDEFINED
D(A1)
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or by GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device; or
GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices.
-6
-7.5
-10
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tDS
1.5
2.0
ns
tCES
1.5
2.0
ns
tAH
0.5
ns
tADSH
0.5
ns
tAAH
0.5
ns
tWH
0.5
ns
tDH
0.5
ns
tCEH
0.5
ns
WRITE TIMING PARAMETERS
-6
-7.5
-10
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tKC
6.0
7.5
10
ns
fKF
166
133
100
MHz
tKH
2.3
2.5
3.0
ns
tKL
2.3
2.5
3.0
ns
tOEHZ
3.5
4.2
4.5
ns
tAS
1.5
2.0
ns
tADSS
1.5
2.0
ns
tAAS
1.5
2.0
ns
tWS
1.5
2.0
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT58L512L18DT-7.5 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
MT58L512L18F 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L512L18FF-10 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
MT58L512L18FF-10IT 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
MT58L512L18FF-7.5 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
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