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參數(shù)資料
| 型號： | MT58L512L18DS-7.5IT |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 4 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026BHA, TQFP-100 |
| 文件頁數(shù)： | 18/31頁 |
| 文件大?。?/td> | 613K |
| 代理商： | MT58L512L18DS-7.5IT |
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8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18D_C.p65 – Rev. 6/01
2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
READ TIMING 3
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
GW#, BWE#,
BWa#-BWd#
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST READ
tOEQ
tOELZ
tKQHZ
Burst wraps around
to its initial state.
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A2 + 3)
A2
A3
(NOTE 1)
Deselect
cycle.
(NOTE 3)
Burst continued with
new base address.
(NOTE 4)
ADV# suspends burst.
DON’T CARE
UNDEFINED
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q
to be driven until after the following clock rising edge.
4. Outputs are disabled within two clock cycles after deselect.
-6
-7.5
-10
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tAS
1.5
2.0
ns
tADSS
1.5
2.0
ns
tAAS
1.5
2.0
ns
tWS
1.5
2.0
ns
tCES
1.5
2.0
ns
tAH
0.5
ns
tADSH
0.5
ns
tAAH
0.5
ns
tWH
0.5
ns
tCEH
0.5
ns
READ TIMING PARAMETERS
-6
-7.5
-10
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tKC
6.0
7.5
10
ns
fKF
166
133
100
MHz
tKH
2.3
2.5
3.0
ns
tKL
2.3
2.5
3.0
ns
tKQ
3.5
4.0
5.0
ns
tKQX
1.5
ns
tKQLZ
0
1.5
ns
tKQHZ
3.5
4.2
5.0
ns
tOEQ
3.5
4.2
5.0
ns
tOELZ
0
ns
tOEHZ
3.5
4.2
4.5
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT58L512L18DT-10IT | 512K X 18 CACHE SRAM, 5 ns, PQFP100 |
| MT58L512L18PB-6IT | 512K X 18 STANDARD SRAM, 3.5 ns, PBGA119 |
| MT58L512L18PS-7.5IT | 512K X 18 CACHE SRAM, 4 ns, PQFP100 |
| MT78740 | RELAY SOCKET |
| MT78745 | RELAY SOCKET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L512L18DT-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18F | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L512L18FF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FF-10IT | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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