參數(shù)資料
型號: MT58L128L36D1T-5IT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 128K X 36 STANDARD SRAM, 2.8 ns, PQFP100
封裝: PLASTIC, MS-026BHA, TQFP-100
文件頁數(shù): 22/23頁
文件大?。?/td> 604K
代理商: MT58L128L36D1T-5IT
8
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18D1.p65 – Rev 12/99
1999, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PRELIMINARY
BGA PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
4P
SA0
Input
Synchronous Address Inputs: These inputs are registered and must
4N
SA1
meet the setup and hold times around the rising edge of CLK.
2A, 3A, 5A,
2A, 2C, 2R,
SA
6A, 3B, 5B,
3A, 3B, 3C,
2C, 3C, 5C,
3T, 4T, 5A,
6C, 2R, 6R,
5B, 5C, 5T,
2T, 3T, 5T, 6T
6A, 6C, 6R
5L
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
3G
5G
BWb#
individual bytes to be written and must meet the setup and hold
3G
BWc#
times around the rising edge of CLK. A byte write enable is LOW
3L
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa;
BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. Parity is only available on the x18
and x36 versions.
4M
BWE#
Input
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
4H
GW#
Input
Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
4K
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
4E
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
6B
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
7T
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When active, all other inputs are ignored.
2B
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded. Pin 6B becomes an SA at 8Mb density.
4F
OE#
Input
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers. Pin 2B becomes an SA at 16Mb density.
4G
ADV#
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on ADV# effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
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