- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385640 > MT58L128L18FT-10 (Micron Technology, Inc.) 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM PDF資料下載
參數(shù)資料
| 型號： | MT58L128L18FT-10 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| 中文描述： | 2MB的：128K的× 18，64K的x 32/36流通過SYNCBURST的SRAM |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 488K |
| 代理商： | MT58L128L18FT-10 |
5
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65
–
Rev. 6/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
37
36
x32/x36
37
36
32-35, 44-49,
81, 82, 99,
100
93
94
95
96
SYMBOL
SA0
SA1
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
32-35, 44-49,
80-82, 99,
100
93
94
–
–
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock
’
s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2
#
. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2
#
is HIGH.
87
87
BWE#
Input
88
88
GW#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
97
97
CE2
Input
86
86
OE#
Input
83
83
ADV#
Input
84
84
ADSP#
Input
(continued on next page)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT58L128L18FT-6.8 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L18FT-7.5 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L18FT-8.5 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128V18FT-10 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128V18FT-6.8 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L128L18FT-10A | 制造商:MAJOR 功能描述: |
| MT58L128L18FT-6.8 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L18FT-7.5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L18FT-8.5 | 制造商:Cypress Semiconductor 功能描述: |
| MT58L128L18PT-10 | 制造商:Cypress Semiconductor 功能描述:128KX18 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。