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參數(shù)資料
| 型號(hào)： | MT55L128V36F1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2.5V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| 中文描述： | 2.5VI / O的128K的× 36，流量通過ZBT SRAM的電壓（2.5V輸入/輸出，4Mb的流通式同步靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 451K |
| 代理商： | MT55L128V36F1 |
7
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
PRELIMINARY
TQFP PIN DESCRIPTIONS (continued)
x18
88
x32/x36
88
SYMBOL TYPE
R/W#
DESCRIPTION
Input
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and the only means for determining
READs and WRITEs. READ cycles may not be converted into
WRITEs (and vice versa) other than by loading a new
address. A LOW on this pin permits BYTE WRITE opera-
tions and must meet the setup and hold times around the
rising edge of CLK. Full bus-width WRITEs occur if all byte
write enables are LOW.
SRAM Data I/Os: Byte
“
a
”
is DQa pins; Byte
“
b
”
is DQb
pins; Byte
“
c
”
is DQc pins; Byte
“
d
”
is DQd pins. Input data
must meet setup and hold times around the rising edge
CLK.
(a)
58, 59, 62, 63,
68, 69, 72-74
(b)
8, 9, 12, 13,
18, 19, 22-24
(a)
52, 53, 56-59,
62, 63
(b)
68, 69, 72-75,
78, 79
(c)
2, 3, 6-9,
12, 13
(d)
18, 19, 22-25,
28, 29
51
80
1
30
31
DQa
Input/
Output
DQb
DQc
DQd
N/A
NC/
DQa
NC/
DQb
NC/
DQc
NC/
DQd
MODE
(LBO#)
NC/
I/O
No Connect/Data Bits: On the x32 version, these pins are
no connect (NC) and can be left floating or connected to
GND to minimize thermal impedance. On the x36 version,
these bits are DQs.
Mode: This input selects the burst sequence. A LOW on
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
No Connect: These pins can be left floating or connected
to GND to minimize thermal impedance.
31
Input
1-3, 6, 7, 25,
28-30, 51-53, 56,
57, 75, 78, 79,
95, 96
83, 84
N/A
NC
NC
83, 84
NF
–
No Function: These pins are internally connected to the
die and will have the capacitance of input pins. It is
allowable to leave these pins unconnected or driven by
signals. Reserved for address expansion, pin 83 becomes
an SA at 8Mb density and pin 84 becomes an SA at 16Mb
density.
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
Power Supply:
See DC Electrical Characteristics and
Operating Conditions for range.
Isolated Output Buffer Supply:
See DC Electrical
Characteristics and Operating Conditions for range.
Ground:
GND.
38, 39, 42, 43
38, 39, 42, 43
DNU
–
15, 16, 41, 65, 91
15, 16, 41, 65, 91
V
DD
Supply
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 14, 17, 21,
26, 40, 55, 60,
66, 67, 71, 76, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 14, 17, 21,
26, 40, 55, 60,
66, 67, 71, 76, 90
V
DD
Q
Supply
V
SS
Supply
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55L128L32P1 | 3.3V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| MT55L128L36P1 | 3.3V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(3.3V或輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| MT55L128V32P1 | 2.5V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| MT55L128V36P1 | 2.5V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| MT55L256L18P1 | 3.3V I/O，256K x 18,Flow-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L128V36P1T-10 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L128V36P1T10A | 制造商:Micron Technology Inc 功能描述: |
| MT55L128V36P1T-6 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT55L128V36P1T-7.5 | 制造商:Micron Technology Inc 功能描述: |
| MT55L1MY18PT-10 | 制造商:Cypress Semiconductor 功能描述:1MX18 SRAM PLASTIC TQFP 3.3V P |
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