參數(shù)資料
型號(hào)： MT55L128L32F1
廠商： Micron Technology, Inc.
英文描述： 3.3V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器)
中文描述： 3.3V的I / O的128K的× 32，流量通過(guò)ZBT SRAM的電壓（3.3V輸入/輸出，4Mb的流通式同步靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 15/25頁(yè)
文件大?。?/td> 451K
代理商： MT55L128L32F1
15
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply
Relative to V
SS
............................... -0.5V to +4.6V
Voltage on V
DD
Q Supply
Relative to V
SS
..........................................-0.5V to V
DD
V
IN
........................................... -0.5V to V
DD
Q + 0.5V
Storage Temperature (plastic) ............-55°C to +150°C
Junction Temperature** ................................... +150°C
Short Circuit Output Current...........................100mA
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Junction temperature depends upon package type,
cycle time, loading, ambient temperature and airflow.
See Micron Technical Note TN-05-14 for more
information.
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0
°
C
￡
T
A
￡
+70
°
C; V
DD
, V
DD
Q = +3.3V ±0.165V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
CONDITIONS
SYMBOL
V
IH
V
IH
V
IL
IL
I
IL
O
MIN
2.0
2.0
-0.3
-1.0
-1.0
MAX
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.0
1.0
UNITS
V
V
V
μA
μA
NOTES
1, 2
1, 2
1, 2
3
DQ pins
0V
￡
V
IN
￡
V
DD
Output(s) disabled,
0V
￡
V
IN
￡
V
DD
I
OH
= -4.0mA
I
OL
= 8.0mA
Output High Voltage
Output Low Voltage
Supply Voltage
Isolated Output Buffer Supply
V
OH
V
OL
V
DD
V
DD
Q
2.4
V
V
V
V
1, 4
1, 4
1
1, 5
0.4
3.465
V
DD
3.135
3.135
NOTE:
1. All voltages referenced to V
SS
(GND).
2. Overshoot:
Undershoot:
Power-up:
3. MODE pin has an internal pull-up, and input leakage = ±10μA.
4. The load used for V
OH
, V
OL
testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O
curves are available upon request.
5. V
DD
Q should never exceed V
DD
. V
DD
and V
DD
Q can be externally wired together to the same power supply for 3.3V I/O
operation.
V
IH
￡
+4.6V for t
￡
t
KHKH/2 for I
￡
20mA
V
IL
-0.7V for t
￡
t
KHKH/2 for I
￡
20mA
V
IH
￡
+3.465V and V
DD
￡
3.135V for t
￡
200ms
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