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參數(shù)資料
| 型號： | MT54W4MH9BF-6 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 36Mb QDR⑩II SRAM 2-WORD BURST |
| 中文描述： | ⑩分配36MB四年防務(wù)審查II SRAM的2字爆 |
| 文件頁數(shù)： | 4/27頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MT54W4MH9BF-6 |
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4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
2002, Micron Technology Inc.
CLOCK CONSIDERATIONS
This device utilizes internal delay-locked loops for
maximum output data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry
automatically resets the DLL when the absence of
input clock is detected. See Micron Technical Note TN-
54-02 for more information on clock DLL start-up pro-
cedures.
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
DEPTH EXPANSION
Port select inputs are provided for the read and
write ports. This allows for easy depth expansion. Both
port selects are sampled on the rising edge of K only.
Each port can be independently selected and dese-
lected and does not affect the operation of the oppo-
site port. All pending transactions are completed prior
to a port deselecting. Depth expansion requires repli-
cating R# and W# control signals for each bank if it is
desired to have the bank independent of READ and
WRITE operations.
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| MT54W4MH9BF-7.5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
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| MT55L128L36F1 | 3.3V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54W4MH9BF-7.5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W512H36BF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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