參數(shù)資料
型號(hào): MT54W4MH9B-7.5
廠商: Micron Technology, Inc.
英文描述: 36Mb QDR⑩II SRAM 2-WORD BURST
中文描述: ⑩分配36MB四年防務(wù)審查II SRAM的2字爆
文件頁數(shù): 16/27頁
文件大小: 302K
代理商: MT54W4MH9B-7.5
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16
2002, Micron Technology Inc.
Hold Times
K rising edge to address
hold
8
K rising edge to control
inputs hold
8
K, K# rising edge to data-in
hold
8
NOTE:
1. Test conditions as specified with the output loading shown in Figure 5, unless otherwise noted.
2. Control input signals may not be operated with pulse widths less than
t
KHKL (MIN).
3. If C and C# are tied HIGH, K and K# become the references for C and C# timing parameters.
4. The device will operate at clock frequencies slower than
t
KHKH (MAX). See Micron Technical Note TN-54-02 for more information.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. V
DD
slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V
DD
and input clock are stable.
7. Echo clock is tightly controlled to data valid/data hold. By design, there is a ±0.1ns variation from echo clock to data. The data sheet
parameters reflect tester guardbands and test setup variations.
8. This is a syncrhonous device. All addresses, data, and control lines must meet the specified setup and hold times for all latching clock
edges.
t
KHAX
0.40
0.50
0.60
0.70
ns
t
KHIX
0.40
0.50
0.70
0.70
ns
t
KHDX
0.40
0.50
0.60
0.70
ns
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING
CONDITIONS
1,
2,
3,
6, 8
0oC T
A
+70oC;
+1.7V V
DD
+1.9V
DESCRIPTION
SYMBOL
-4
-5
-6
-7.5
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
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