參數(shù)資料
型號: MT54W4MH9B-6
廠商: Micron Technology, Inc.
英文描述: 36Mb QDR⑩II SRAM 2-WORD BURST
中文描述: ⑩分配36MB四年防務(wù)審查II SRAM的2字爆
文件頁數(shù): 13/27頁
文件大小: 302K
代理商: MT54W4MH9B-6
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
13
2002, Micron Technology Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply
Relative to V
SS
........................................ 0.5V to +2.8V
Voltage on V
DD
Q Supply
Relative to V
SS
.......................................-0.5V to +V
DD
V
IN
.....................................................-0.5V to V
DD
+ 0.5V
Storage Temperature..............................-55oC to +125oC
Junction Temperature**....................................... +125oC
Short Circuit Output Current .............................. ±70mA
*Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
**Maximum junction temperature depends upon package
type, cycle time, loading, ambient temperature, and airflow.
See Micron Technical Note TN-05-14 for more information.
NOTE:
1. Outputs are impedance-controlled. |I
OH
| = (V
DD
Q/2)/(RQ/5) for values of 175 RQ 350 .
2. Outputs are impedance-controlled. I
OL
= (V
DD
Q/2)/(RQ/5) for values of 175 RQ 350 .
3. All voltages referenced to V
SS
(GND).
4. Overshoot:
V
IH
(
AC
) V
DD
+ 0.7V for t
t
KHKH/2
Undershoot: V
IL
(
AC
) -0.5V for t
t
KHKH/2
Power-up:
V
IH
V
DD
Q + 0.3V and V
DD
1.7V and V
DD
Q 1.4V for t 200ms
During normal operation, V
DD
Q must not exceed V
DD
. Control input signals may not have pulse widths less than
t
KHKL
(MIN) or operate at cycle rates less than
t
KHKH (MIN).
5. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
6. Output buffer supply can be set to 1.5V or 1.8V nominal ±0.1 with appropriate derating of AC timing parameters. Consult factory for
further information.
7. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
8. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, V
IL
(
AC
) or V
IH
(
AC
).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, V
IL
(
DC
) or V
IH
(
DC
).
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
0oC T
A
+70oC;
+1.7V V
DD
+1.9V unless otherwise noted
DESCRIPTION
CONDITIONS
SYMBOL
V
IH
(
DC
)
V
IL
(
DC
)
V
IN
IL
I
IL
O
MIN
MAX
UNITS
V
V
V
μA
μA
NOTES
3, 4
3, 4
3, 4
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Clock Input Signal Voltage
Input Leakage Current
Output Leakage Current
V
REF
+ 0.1
-0.3
-0.3
-5
-5
V
DD
Q + 0.3
V
REF
- 0.1
V
DD
Q + 0.3
5
5
0V V
IN
V
DD
Q
Output(s) disabled,
0V V
IN
V
DD
Q (Q)
|
I
OH
|
0.1mA
Note 1
I
OL
0.1mA
Note 2
Output High Voltage
V
OH
(
LOW
)
V
OH
V
OL
(
LOW
)
V
OL
V
DD
V
DD
Q
V
REF
V
DD
Q - 0.2
V
DD
Q/2 - 0.12
V
SS
V
DD
Q/2 - 0.12
1.7
1.4
0.68
V
DD
Q
V
V
V
V
V
V
V
3, 5, 7
3, 5, 7
3, 5, 7
3, 5, 7
3
3, 6
3
V
DD
Q/2 + 0.12
0.2
V
DD
Q/2 + 0.12
1.9
V
DD
0.95
Output Low Voltage
Supply Voltage
Isolated Output Buffer Supply
Reference Voltage
AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
0oC T
A
+70oC;
+1.7V V
DD
+1.9V unless otherwise noted
DESCRIPTION
CONDITIONS
SYMBOL
V
IH
AC
)
MIN
MAX
UNITS
V
NOTES
3, 4, 8
Input High (Logic 1) Voltage
V
REF
+ 0.2
Input Low (Logic 0) Voltage
V
IL
(
AC
)
V
REF
- 0.2
V
3, 4, 8
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