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參數(shù)資料
| 型號(hào)： | MT54W4MH9B-4 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 36Mb QDR⑩II SRAM 2-WORD BURST |
| 中文描述： | ⑩分配36MB四年防務(wù)審查II SRAM的2字爆 |
| 文件頁數(shù)： | 12/27頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MT54W4MH9B-4 |
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4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
12
2002, Micron Technology Inc.
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. means rising edge; means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C and C# are
HIGH, then data outputs are delivered at K and K# rising edges.
3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming
transmission line charging symmetrically.
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation, provided that
the setup and hold requirements are satisfied.
8. This table illustrates operation for the x18 devices. The x36 device operation is similar, except for the addition of BW2# (controls
D18:D26) and BW3# (controls D27:D35). The x9 device operation is similar, except that BW1# and D8:D17 are not available. The x8
device operation is similar, except that NW0# controls D0:D3, and NW1# controls D4:D7.
TRUTH TABLE
Notes 1-6
OPERATION
K
R#
X
W#
L
D or Q
D
A
(A + 0)
at
K(t)
Q
A
(A + 0)
at
C#(t + 1)
D = X
Q = High-Z
Previous
State
D or Q
D
A
(A + 1)
at
K
#(
t
)
Q
A
(A + 1)
at
C(t + 2)
D = X
Q = High-Z
Previous
State
WRITE Cycle:
Load address, input write data on
consecutive K and K# rising edges
READ Cycle:
Load address, output data on
consecutive C and C# rising edges
NOP: No operation
L
H
L
H
L
X
L
H
H
H
STANDBY: Clock stopped
Stopped
X
X
BYTE WRITE OPERATION
Notes 7, 8
OPERATION
K
K#
BW0#
0
0
0
0
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
WRITE D0-17 at K rising edge
WRITE D0-17 at K# rising edge
WRITE D0-8 at K rising edge
WRITE D0-8 at K# rising edge
WRITE D9-17 at K rising edge
WRITE D9-17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT54W4MH9B-5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-6 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-7.5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-4 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54W4MH9B-5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-7.5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9BF-5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
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